Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
TMMR
Register Description:
Transmit Master Mode Register
Register Address:
base address + 0x600
Bit # 7 6 5 4 3 2 1 0
Name FRM_EN INIT_DONE - - - - SFTRST E1/T1
Default 0 0 0 0 0 0 0 0
Bit 7: Formatter Enable (FRM_EN). This bit must be set to the desired state before setting the INIT_DONE bit.
0 = Framer disabled – held in low-power state
1 = Framer enabled – all features active
Bit 6: Initialization Done (INIT_DONE). The CPU must set the E1/T1 and FRM_EN bits prior to setting this bit.
After INIT_DONE is set, the transmitter is enabled if FRM_EN = 1.
Bit 1: Soft Reset (SFTRST). Level sensitive reset. Should be set to 1, then to 0 to reset and initialize the transmit
formatter .
0 = Normal operation
1 = Reset the transmit formatter in reset
Bit 0: Transmitter E1/T1 Mode Select (E1/T1). This bit specifies the operating mode for the transmit formatter
only. The RMMR:E1/T1 bit
specifies the operating mode for the receive framer. This bit must be set to the desired
value before setting the INIT_DONE bit.
0 = T1 operation
1 = E1 operation
Register Name:
TCR1-T1
Register Description:
Transmit Control Register 1 (T1 Mode)
Register Address:
base address + 0x604
Bit # 7 6 5 4 3 2 1 0
Name TJC TFPT TCPT TSSE GB7S TB8ZS TAIS TRAI
Default 0 0 0 0 0 0 0 0
Bit 7: Transmit Japanese CRC-6 Enable (TJC).
0 = Use ANSI/AT&T:ITU CRC-6 calculation (normal operation)
1 = Use Japanese standard JT–G704 CRC-6 calculation
Bit 6: Transmit F–Bit Pass Through (TFPT).
0 = F bits sourced internally
1 = F bits sampled at framer input TSER
Bit 5: Transmit CRC Pass Through (TCPT).
0 = Source CRC-6 bits internally
1 = Sample CRC-6 bits at framer input TSER during F-bit times
Bit 4: Transmit Software Signaling Enable (TSSE).
0 = Do not source signaling data from the TS regi
sters regardless of the TSSIE registers. The TSSIE
registers can still define which channels are to have bit 7 stuffing performed (when TCR1-T1.GB7S=
0).
1 = Source signaling data as enabled by the TSSIE registers. See
section 10.11.3.1.1.
Bit 3: Glo
bal Bit 7 Stuffing (GB7S). When TCR2-T1.TB7ZS=0, n
o bit 7 stuffing occurs and this bit is ignored.
0 = Allow the TSSIE registers
to determine which channels containing all zeros are to be bit 7 stuffed
1 = Force bit 7 stuffing in all zero byte channels of the port, regardless of how the TSSIE registers
are
configured.