Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
TAF
Register Description:
Transmit Align Frame (E1 Mode)
Register Address:
base address + 0x590
Bit # 7 6 5 4 3 2 1 0
Name Si 0 0 1 1 0 1 1
Default 0 0 0 1 1 0 1 1
Note: This register has an alternate definition for T1 mode. See TSLC1.
The alig
n frame is the E1 frame containing the frame alignment signal (FAS). The bits of this register specify the
first eight bits of the align frame in the outgoing E1 data stream. The bits are sampled from this register at the start
of the align frame, which is indicated by the TAF status bit in TLS1.
Various control fields can cause some of these
bits to be sourced from elsewhere. See Section 10.11.5.1.
Bit 7: International Bit (Si
).
Bits 6 to 0: Frame Alignment Signal (FAS[6:0]. Should be set to 0011011 for normal E1 operation.
Register Name:
TNAF
Register Description:
Transmit Non-Align Frame (E1 Mode)
Register Address:
base address + 0x594
Bit # 7 6 5 4 3 2 1 0
Name Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8
Default 0 1 0 0 0 0 0 0
The non-align frame is the E1 frame that does not contain the frame alignment signal (FAS). The bits of this
register specify the first eight bits of the non-align frame in the outgoing E1 data stream. The bits are sampled from
this register at the start of the align frame, which is indicated by the TAF status bit in TLS1.
Various control fields
can cause some of these bits to be sourced from elsewhere. See Section 10.11.5.1.
Bit 7: International Bit (Si
).
Bit 6: Non-Align Frame Signal Bit. Should be set to 1 for normal E1 operation.
Bit 5: Remote Alarm Indication (RAI). This is the normal control bit for manipulating the RAI bit in the outgoing E1
frames.
0 = No alarm condition
1 = Alarm condition
Bits 4 to 0: Additional Spare Bits (Sa4 to Sa8).