Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
TCICE1, TCICE2, TCICE3, TCICE4
Register Description:
Transmit Channel Idle Code Enable Registers
Register Address:
base address + 0x540, 0x544, 0x548, 0x54C
Bit # 7 6 5 4 3 2 1 0
TCICE1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
TCICE2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
TCICE3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
TCICE4 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
Bits 7 to 0 (x4): Transmit Idle Code Insertion Enable for Channels 1 to 32 (CH1 to CH32). See section
10.11.12.
0 = Do n
ot insert data from the idle code array (TIDR regi
sters) into the transmit data stream
1 = Insert data from the idle code array into the transmit data stream
Register Name:
TFDL
Register Description:
Transmit FDL Register (T1 Mode Only)
Register Address:
base address + 0x588
Bit # 7 6 5 4 3 2 1 0
Name TFDL7 TFDL6 TFDL5 TFDL4 TFDL3 TFDL2 TFDL1 TFDL0
Default 0 0 0 0 0 0 0 0
Bits 7 to 0: Transmit FDL (TFDL[7:0]). In ESF mode this register holds the facility data link (FDL) information that
is inserted into the outgoing data stream. The LSb is transmitted first. In SF mode, bits [5:0] hold the Fs framing
pattern that is inserted into the outgoing data stream. Bit 7 is the MSb. See section 10.11.4.3 and
section 10.11.16.
Register Name:
TBOC
Register Description:
Transmit Bit-Oriented Code Register (T1 Mode Only)
Register Address:
base address + 0x58C
Bit # 7 6 5 4 3 2 1 0
Name - - TBOC5 TBOC4 TBOC3 TBOC2 TBOC1 TBOC0
Default 0 0 0 0 0 0 0 0
Bits 5 to 0: Transmit Bit-Oriented Code (TBOC[5:0]). T1 ESF mode only. This register holds the bit-oriented
code (BOC) information that is inserted into the outgoing data stream. The LSb (TBOC0) is transmitted first. See
Section 10.11.4.1.
Register Name :
TSLC1, TSLC2, TSLC3
Register Description:
Transmit SLC96 Data Link Registers (T1 Mode)
Register Address:
base address + 0x590, 0x594, 0x598
Bit # 7 6 5 4 3 2 1 0
T1TSLC1 C8 C7 C6 C5 C4 C3 C2 C1
T1TSLC2 M2 M1 S=0 S=1 S=0 C11 C10 C9
T1TSLC3 S=1 S4 S3 S2 S1 A2 A1 M3
Note: These registers have an alternate definition for E1 mode. See TAF, TNAF, and TSiAF.
See se
ction 10.11.16.