Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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9 PIN DESCRIPTIONS
9.1 Short Pin Descriptions
Table 9-1. Short Pin Descriptions
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
Internal E1/T1 LIU Line Interface
TXENABLE I LIU Transmit Enable Input (for all LIUs)
TTIPn, TRINGn Oa LIU Transmitter Analog Outputs
RTIPn, RRINGn Ia LIU Receiver Analog Inputs
RXTSEL I Receive Termination Selection Input (for All LIUs)
RESREF I
Reference Resistor for LIU Analog Circuits (precision 10k to ARVSS)
External E1/T1 LIU Interface
TCLKOn O Transmit Clock Output
TDATFn O Transmit Data Output
RCLKFn / RCLKn IO Receive Clock Input to Framer (RCLKFn)
or Recovered Clock Output from LIU Receiver (RCLKn)
RDATFn I Receive Data Input to Framer
Framer TDM Interface
TCLKFn I Transmit Clock Input to Formatter
TSYSCLKn / ECLKn I Transmit System Clock Input (clock for cross-connect side of elastic store)
or External Reference Clock Input
TSERn I Transmit Serial Data Input
TSYNCn / TSSYNCn IO Transmit Frame/Multiframe Sync Input/Output or Transmit System
Frame/Multiframe Sync Input (sync for cross-connect side of elastic store)
RSYSCLKn I Receive System Clock Input (clock for cross-connect side of elastic store)
RSERn O Receive Serial Data Output
RSYNCn IO Receive Frame/Multiframe Sync Input/Output
RFSYNCn/ RMSYNCn O Receive Frame Sync or Receive Multiframe Sync Output
RLOFn/ RLOSn O Receive Loss of Frame Output or Receive Loss of Signal Output
TDM-over-Packet Engine TDM Interface
TDMn_ACLK O TDMoP Recovered Clock Output
TDMn_TCLK Ipu TDMoP Transmit Clock Input (here transmit means “toward LIU”)
TDMn_TX O TDMoP Transmit Data Output
TDMn_TX_SYNC Ipd TDMoP Transmit Frame Sync Input
TDMn_TX_MF_CD IOpd TDMoP Transmit Multiframe Sync Input or Carrier Detect Output
TDMn_TSIG_CTS O TDMoP Transmit Signaling Output or Clear to Send Output
TDMn_RCLK Ipu TDMoP Receive Clock Input (here receive means “toward Ethernet MII”)
TDMn_RX Ipu TDMoP Receive Data Input
TDMn_RX_SYNC Ipd TDMoP Receive Frame/Multiframe Sync Input
TDMn_RSIG_RTS Ipu TDMoP Receive Signaling Input or Request To Send Input
SDRAM Interface
SD_CLK O SDRAM Clock
SD_D[31:0] IO SDRAM Data Bus
SD_DQM[3:0] O SDRAM Byte Enable Mask
SD_A[11:0] O SDRAM Address Bus
SD_BA[1:0] O SDRAM Bank Select Outputs
SD_CS_N O SDRAM Chip Select (Active Low)
SD_WE_N O SDRAM Write Enable (Active Low)
SD_RAS_N O SDRAM Row Address Strobe (Active Low)
SD_CAS_N O SDRAM Column Address Strobe (Active Low)
Ethernet PHY Interface (MII/RMII/SSMII)
CLK_MII_TX I MII Transmit Clock Input
CLK_SSMII_TX O SSMII Transmit Clock Output
MII_TXD[3:0] O MII Transmit Data Outputs
MII_TX_EN O MII Transmit Enable Output
MII_TX_ERR O MII Transmit Error Output