Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
279 of 366
Register Name:
TS1 to TS16
Register Description:
Transmit Signaling Registers
Register Address:
base address + 0x500 + 0x04*(n-1), n = 1 to 16
T1 Mode:
Bit # 7 6 5 4 3 2 1 0
TS1 CH1-A CH1-B CH1-C CH1-D CH13-A CH13-B CH13-C CH13-D
TS2 CH2-A CH2-B CH2-C CH2-D CH14-A CH14-B CH14-C CH14-D
TS3 CH3-A CH3-B CH3-C CH3-D CH15-A CH15-B CH15-C CH15-D
TS4 CH4-A CH4-B CH4-C CH4-D CH16-A CH16-B CH16-C CH16-D
TS5 CH5-A CH5-B CH5-C CH5-D CH17-A CH17-B CH17-C CH17-D
TS6 CH6-A CH6-B CH6-C CH6-D CH18-A CH18-B CH18-C CH18-D
TS7 CH7-A CH7-B CH7-C CH7-D CH19-A CH19-B CH19-C CH19-D
TS8 CH8-A CH8-B CH8-C CH8-D CH20-A CH20-B CH20-C CH20-D
TS9 CH9-A CH9-B CH9-C CH9-D CH21-A CH21-B CH21-C CH21-D
TS10 CH10-A CH10-B CH10-C CH10-D CH22-A CH22-B CH22-C CH22-D
TS11 CH11-A CH11-B CH11-C CH11-D CH23-A CH23-B CH23-C CH23-D
TS12 CH12-A CH12-B CH12-C CH12-D CH24-A CH24-B CH24-C CH24-D
E1 Mode :
Bit # 7 6 5 4 3 2 1 0
TS1 0 0 0 0 X Y X X
TS2 CH1-A CH1-B CH1-C CH1-D CH16-A CH16-B CH16-C CH16-D
TS3 CH2-A CH2-B CH2-C CH2-D CH17-A CH17-B CH17-C CH17-D
TS4 CH3-A CH3-B CH3-C CH3-D CH18-A CH18-B CH18-C CH18-D
TS5 CH4-A CH4-B CH4-C CH4-D CH19-A CH19-B CH19-C CH19-D
TS6 CH5-A CH5-B CH5-C CH5-D CH20-A CH20-B CH20-C CH20-D
TS7 CH6-A CH6-B CH6-C CH6-D CH21-A CH21-B CH21-C CH21-D
TS8 CH7-A CH7-B CH7-C CH7-D CH22-A CH22-B CH22-C CH22-D
TS9 CH8-A CH8-B CH8-C CH8-D CH23-A CH23-B CH23-C CH23-D
TS10 CH9-A CH9-B CH9-C CH9-D CH24-A CH24-B CH24-C CH24-D
TS11 CH10-A CH10-B CH10-C CH10-D CH25-A CH25-B CH25-C CH25-D
TS12 CH11-A CH11-B CH11-C CH11-D CH26-A CH26-B CH26-C CH26-D
TS13 CH12-A CH12-B CH12-C CH12-D CH27-A CH27-B CH27-C CH27-D
TS14 CH13-A CH13-B CH13-C CH13-D CH28-A CH28-B CH28-C CH28-D
TS15 CH14-A CH14-B CH14-C CH14-D CH29-A CH29-B CH29-C CH29-D
TS16 CH15-A CH15-B CH15-C CH15-D CH30-A CH30-B CH30-C CH30-D
In the T1 ESF framing mode, there can be up to four signaling bits per channel (A, B, C, and D). In the T1 SF (D4)
framing mode, there are only two signaling bits per channel (A and B); the C and D bit positions are ignored. See
section 10.11.3.1.1.