Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Bit 1: Additional Bit 7 Insertion Control Bit (Sa7).
0 = Do not insert data from the TSa7 registe
r into the transmit data stream
1 = Insert data from the TSa7 regi
ster into the transmit data stream
Bit 0: Additional Bit 8 Insertion Control Bit (Sa8).
0 = Do not insert data from the TSa8 registe
r into the transmit data stream
1 = Insert data from the TSa8 regi
ster into the transmit data stream
Register Name :
TSSIE1, TSSIE2, TSSIE3, TSSIE4
Register Description:
Transmit Software Signaling Insertion Enable Registers
Register Address:
base address + 0x460, 0x464, 0x468, 0x46C
Bit # 7 6 5 4 3 2 1 0
SSIE1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
SSIE2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
SSIE3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
SSIE4 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
Bits 7 to 0: Software Signaling Insertion Enable for Channels 1 to 32 (SSIEx). When TCR1-T1.TSSE=1, thes
e
bits determine which DS0 channels are to have signaling inserted form the transmit signaling registers (TS1
throug
h TS16). Whe
n TCR1-T1.TSSE=0, these bits are ignored. In addition, in T1 mode, when TCR2-T1.TB7ZS=1
and TCR1-T1.GB7S=0
these bits specify which channels are bit-7 stuffed when all-zeros occurs. In E1 mode,
when TCR1-E1.T16S=0 t
hese bits determine which DS0 channels are to have signaling inserted form the TS
registers. When T16S=1, these bits are ignored. See section 10.11.3.1.1.
0 = Do not source signaling data from the transmit signaling register for this channel.
1 = Source signaling data from the transmit signaling register for this channel.
Register Name:
TIDR1 to TIDR32
Register Description:
Transmit Idle Code Definition Registers 1 to 32
Register Address:
base address + 0x480 + 0x04*(n-1), n = channel number = 1 to 32
Bit # 7 6 5 4 3 2 1 0
Name C7 C6 C5 C4 C3 C2 C1 C0
Default 0 0 0 0 0 0 0 0
Bits 7 to 0: Per-Channel Idle Code Bits (C[7:0]). C0 is the LSB of the code (this bit is transmitted last). Address
0x480 holds the idle code for channel 1. Address 0x4DC is for channel 24. Address 0x4FC is for channel 32. Note
that TIDR25 to TIDR32 are only for E1 mode. See section 10.11.12.