Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Bit 5: Transmit HDLC Reset (THR). A low-to-high transition of this bit resets the Tx HDLC controller and flushes
the Tx HDLC FIFO. The Tx HDLC controller transmits an abort followed by intermessage fill (determined by the
THC1.TFS b
it) until a new packet transmission is initiated by writing new data into the FIFO. This is an
acknowledged reset, that is, the CPU sets the bit to cause the reset, and the device clears the bit once the reset
operation is complete. Total time for the reset is less than 250
s. See section 10.12.2.
0 = Normal operation
1 = Reset Tx HDLC controller and flush the Tx HDLC FIFO
Bit 4: Transmit HDLC Mapping Select (THMS). See section 10.12.2.
0 = Tx HD
LC assigned to DS0 channel(s)
1 = Tx HDLC assigned to FDL (T1 mode) or Sa Bits (E1 mode).
Bit 3: Transmit Flag/Idle Select (TFS). This bit selects the inter-message fill character after the closing and before
the opening flags (7Eh). See section 10.12.2.
0 = 0x7E
1 = 0xFF
Bit 2
: Transmit End of Message (TEOM). This bit must be set to a one just before the last data byte of an HDLC
packet is written into the transmit FIFO at THF. If n
ot disabled via THC1.TCRCD, the transmitter automatically
appends a two-byte CRC code to the end of the message. See section 10.12.2.
Bit 1
: Transmit Zero Stuffer Defeat (TZSD). The zero stuffer function automatically inserts a zero in the message
field (between the flags) after 5 consecutive ones to prevent the emulation of a flag or abort sequence by the data
pattern. The receiver automatically removes (de-stuffs) any zero after 5 ones in the message field. See section
10.12.2.
0 = ena
ble the zero stuffer (normal operation)
1 = disable the zero stuffer
Bit 0: Transmit CRC Defeat (TCRCD). In normal operation a two-byte CRC code is automatically appended to
the outbound message. This bit can be used to disable the CRC generation function. See section 10.12.2.
0 = ena
ble CRC generation (normal operation)
1 = disable CRC generation
Register Name:
THBSE
Register Description:
Transmit HDLC Bit Suppress Register
Register Address:
base address + 0x444
Bit # 7 6 5 4 3 2 1 0
Name TBSE8 TBSE7 TBSE6 TBSE5 TBSE4 TBSE3 TBSE2 TBSE1
Default 0 0 0 0 0 0 0 0
Bits 7 to 0: Receive Bit Suppress 8 to 1 (BSE[8:1]). These bits specify whether the corresponding bit of the DS0
channel should be included or excluded (suppressed) in carrying the data stream generated by the transmit HDLC
controller. BSE8 is the MSb of the channel. See section 10.12.2.
0 = Include this bit in the data stream
1= Don’t include (suppress) this bit