Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
TJBE1, TJBE2, TJBE3, TJBE4
Register Description:
Transmit Jammed Bit Eight Registers
Register Address:
base address + 0x410, 0x404, 0x410, 0x41C
Bit # 7 6 5 4 3 2 1 0
TJBE1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
TJBE2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
TJBE3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
TJBE4 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
Bits 7 to 0: Transmit Jammed Bit Eight Stuffing Control Bits for Channels 1 to 32 (CH1 to CH32). These
registers are enabled by TCR4.TJBEN.
CH25 through CH32 are only used in E1 mode. Transmit jammed bit eight,
also known as GTE zero code suppression, is a pulse density enforcement mechanism. When jammed bit eight is
enabled for a channel, in any frame where all eight bits of the channel are zero, bit 8 (bit 7 in T1 signaling frames)
is set to 1.
0 = Do not affect the transmit data associated with this channel
1 = Set bit 8 (bit 7 in T1 signaling frames) to 1 when all eight bits of the channel are zero
Register Name:
TDDS1, TDDS2, TDDS3
Register Description:
Transmit DDS Zero Code Registers (T1 Mode Only)
Register Address:
base address + 0x420, 0x424, 0x428
Bit # 7 6 5 4 3 2 1 0
TDDS1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
TDDS2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
TDDS3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
Bits 7 to 0: Transmit DDS Zero Code Control Bits for Channels 1 to 24 (CH1 to CH24). These registers are
enabled by TCR2.TD
DSEN. DDS is a pulse density enforcement mechanism. When DDS is enabled for a channel,
in any frame where all eight bits of the channel are zero, the channel data is replaced with 10011000b.
0 = Do not affect the transmit data associated with this channel
1 = Replace channel data with 10011000b when all eight bits of the channel are zero
Register Name:
THC1
Register Description:
Transmit HDLC Control Register 1
Register Address:
base address + 0x440
Bit # 7 6 5 4 3 2 1 0
Name NOFS TEOML THR THMS TFS TEOM TZSD TCRCD
Default 0 0 0 0 0 0 0 0
Bit 7: Number Of Flags Select (NOFS). See section 10.12.2.
0 = se
nd one flag between consecutive messages
1 = send two flags between consecutive messages
Bit 6: Transmit End of Message and Loop (TEOML). The term “loop” means to transmit the message repeatedly
until instructed to stop. To loop on a message, set this bit to one just before the last data byte of an HDLC packet is
written into the transmit FIFO. The Tx HDLC controller then repeats the message until the CPU clears this bit or a
new message is written to the Tx HDLC FIFO. When the CPU clears this bit, the HDLC controller transmits the
remainder of the in-progress copy of the message and then transmits flags until a new message is written to the Tx
HDLC FIFO. If the CPU ends the loop by writing a new message to the FIFO, the Tx HDLC controller ends the
loop, transmits one or two flags and then transmits the new message. If not disabled via THC1.TCRCD
, the Tx
HDLC controller automatically appends a two-byte CRC code to the end of all messages. See section 10.12.2.