Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Addr
Offset
Register Name Description
Read/Write or
Read Only
Page
67C TIIR Tx Interrupt Information Register R/W 298
680 TIM1 Tx Interrupt Mask Register 1 R/W 298
684 TIM2 Tx Interrupt Mask Register 2 (HDLC) R/W 299
688 TIM3 Tx Interrupt Mask Register 3 (SYNC) R/W 299
6B0 TCD1 Tx Code Definition Register 1 (T1 Mode Only) R/W 300
6B4 TCD2 Tx Code Definition Register 2 (T1 Mode Only) R/W 300
6C4 TRTS2 Tx Real-Time Status Register 2 (HDLC) R 300
6CC TFBA Tx HDLC FIFO Buffer Available Register R 301
6D0 THF Tx HDLC FIFO Register W 301
6EC TDS0M Tx DS0 Monitor Register R 301
700 TBCS1 Tx Blank Channel Select Register 1 R/W 302
704 TBCS2 Tx Blank Channel Select Register 2 R/W 302
708 TBCS3 Tx Blank Channel Select Register 3 R/W 302
70C TBCS4 Tx Blank Channel Select Register 4 (E1 Mode Only) R/W 302
720 THSCS1 Tx Hardware Signaling Channel Select 1 R/W 302
724 THSCS2 Tx Hardware Signaling Channel Select 2 R/W 302
728 THSCS3 Tx Hardware Signaling Channel Select 3 R/W 302
72C THSCS4 Tx Hardware Signaling Channel Select 4 (E1 Only) R/W 302
740 PCL1 Per-Channel Loopback Enable Register 1 R/W 302
744 PCL2 Per-Channel Loopback Enable Register 2 R/W 302
748 PCL3 Per-Channel Loopback Enable Register 3 R/W 302
74C PCL4 Per-Channel Loopback Enable Register 4 (E1 Only) R/W 302
750 TBPCS1 Tx BERT Port Channel Select Register 1 R/W 303
754 TBPCS2 Tx BERT Port Channel Select Register 2 R/W 303
758 TBPCS3 Tx BERT Port Channel Select Register 3 R/W 303
75C TBPCS4 Tx BERT Port Channel Select Register 4 (E1 Only) R/W 303
Register Name :
TDMWE1, TDMWE2, TDMWE3, TDMWE4
Register Description:
Transmit Digital Milliwatt Enable Registers (E1 and T1)
Register Address:
base address + 0x400, 0x404, 0x408, 0x40C
Bit # 7 6 5 4 3 2 1 0
TDMWE1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
TDMWE2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
TDMWE3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
TDMWE4 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
Bits 7 to 0 (x4): Transmit Digital Milliwatt Enable for Channels 1 to 32 (CH1 to CH32). Configuration bit
TCR4.uALA
W specifies whether u-law coding or A-law coding is used. See section 10.11.13.
0 = Do not affect the transmit data associated with this channel
1 = Replace the transmit data associated with this channel with digital milliwatt code