Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
RCICE1, RCICE2, RCICE3, RCICE4
Register Description:
Receive Channel Idle Code Enable Registers
Register Address:
base address + 0x340, 0x344, 0x348, 0x34C
Bit # 7 6 5 4 3 2 1 0
RCICE1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
RCICE2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
RCICE3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
RCICE4 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
Bits 7 to 0 (x4): Receive Idle Code Insertion Enable for Channels 1 to 32 (CH1 to CH32). See section
10.11.12.
0 = Do n
ot insert data from the idle code array (RIDR regi
sters) into the receive data stream.
1 = Insert data from the idle code array into the receive data stream
Register Name:
RBPCS1, RBPCS2, RBPCS3, RBPCS4
Register Description:
Receive BERT Port Channel Select Registers
Register Address:
base address + 0x350, 0x354, 0x358, 0x35C
Bit # 7 6 5 4 3 2 1 0
RBPCS1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
RBPCS2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
RBPCS3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
RBPCS4 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
Bits 7 to 0 (x4): Receive BERT Port Channel Select for Channels 1 to 32 (CH1 to CH32). These bits specify for
which channels data is forwarded to the receive BERT. Any combination of channels may be selected
simultaneously. See section 10.14.3.
0 = Do n
ot map the selected channel to the receive BERT port.
1 = Map the selected channel to the receive BERT Port.