Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
RHF
Register Description:
Receive HDLC FIFO Register
Register Address:
base address + 0x2D8
Bit # 7 6 5 4 3 2 1 0
Name RHD7 RHD6 RHD5 RHD4 RHD3 RHD2 RHD1 RHD0
Default 0 0 0 0 0 0 0 0
Bit 7 to 0: Receive HDLC Data (RHD[7:0]). A read of this register returns the next byte in the receive HDLC FIFO.
Bit 7 is the MSb. This register is read-only. See section 10.12.1.
Register Name:
RBCS1, RBCS2, RBCS3, RBCS4
Register Description:
Receive Blank Channel Select Registers
Register Address:
base address + 0x300, 0x304, 0x308, 0x30C
Bit # 7 6 5 4 3 2 1 0
RBCS1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
RBCS2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
RBCS3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
RBCS4 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
Default 0 0 0 0 0 0 0 0
Bit 7 to 0 (x4): Receive Blank Channel Select for Channels 1 to 32 (CH1 to CH32).
0 = do not blank this channel (channel data is available on RSER)
1 = data on RSER is forced to all ones for this channel
Note that when two or more sequential channels are chosen to be blanked, the receive slip zone select bit
(RESCR.RSZS) shoul
d be set to zero. If the blank channels are distributed (such as 1, 5, 9, 13, 17, 21, 25, 29)
then the RSZS bit can be set to one, which may provide a lower occurrence of slips in certain applications.
Register Name:
RSI1, RSI2, RSI3, RSI4
Register Description:
Receive Signaling Reinsertion Enable Registers
Register Address:
base address + 0x320, 0x324, 0x328, 0x32C
Bit # 7 6 5 4 3 2 1 0
RSI1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
RSI2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
RSI3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
RSI4 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
Default 0 0 0 0 0 0 0 0
Bit 7 to 0 (x4): Receive Signaling Reinsertion Enable for Channels 1 to 32 (CH1 to CH32). Setting any of
these bits to one causes signaling data to be reinserted for the associated channel. RSI4 is used for 2.048MHz
system TDM interface operation. See Section 10.11.3.2.