Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
RRTS5
Register Description:
Receive Real-Time Status Register 5 (HDLC)
Register Address:
base address + 0x2D0
Bit # 7 6 5 4 3 2 1 0
Name - PS2 PS1 PS0 - - RHWM RNE
Default 0 0 0 0 0 0 0 0
These bits provide real-time status information from the receive framer.
Bits 6 to 4: Receive Packet Status (PS[2:0]). This field indicates Rx HDLC status as of the last FIFO read. See
section 10.12.1.
PS2 PS1
PS0 PACKET STATUS
0 0 0 In Progress: End of message has not yet been reached.
0 0 1 Packet OK: Packet ended with correct CRC codeword.
0 1 0
CRC Error: A closing flag was detected, preceded by a corrupt CRC codeword.
0 1 1
Abort: Packet ended because abort signal was detected. (7 or more ones in a
row).
1 0 0
Overrun: HDLC controller terminated reception of packet because receive
FIFO is full.
Bit 1: Receive FIFO Above High Watermark Condition (RHWM). Set when the 64-byte receive FIFO fills beyond
the high watermark set by RHFC.R
FHWM. See section 10.12.1.
Bit 0:
Receive FIFO Not Empty Condition (RNE). Set when the 64-byte receive FIFO has at least one byte
available to be read. See section 10.12.1.
Register Name:
RHPBA
Register Description:
Receive HDLC Packet Bytes Available Register
Register Address:
base address + 0x2D4
Bit # 7 6 5 4 3 2 1 0
Name MS RPBA6 RPBA5 RPBA4 RPBA3 RPBA2 RPBA1 RPBA0
Default 0 0 0 0 0 0 0 0
Bit 7: Message Status (MS). This bit has is set to 1 when the Rx HDLC FIFO is empty. See section 10.12.1.
0 =
Bytes indicated by RPBA[6:0] are the end of a message. The CPU must check the HDLC status
register (RRTS5) for detail
s.
1 = Bytes indicated by RPBA[6:0] are the beginning or continuation of a message. The CPU does not need
to check the HDLC status.
Bits 6 to 0: Receive FIFO Packet Bytes Available Count (RPBA[6:0]). This field indicates the number of bytes
available to be read in the receive HLDC FIFO (RHF)
. RPBA0 is the LSb. See section 10.12.1.