Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
RRTS3-T1
Register Description:
Receive Real-Time Status Register 3 (T1 Mode)
Register Address:
base address + 0x2C8
Bit # 7 6 5 4 3 2 1 0
Name -- -- -- -- LORC LSP LDN LUP
Default 0 0 0 0 0 0 0 0
Note: This register has an alternate definition for E1 mode. See RRTS3-E1.
These bits p
rovide real-time status information from the receive framer.
Bit 3: Loss of Receive Clock Condition (LORC). Set when the RCLK pin has not transitioned for one channel
time.
Bit 2: Spare Code Detected Condition (LSP). Set when the spare code as defined in the RSCD1 an
d RSCD2
registers is being received.
Bit 1: Loop Down Code Detected Condition (LDN). Set when the loop down code as defined in the RDNCD1
and RDNCD2 r
egisters is being received.
Bit 0: Loop Up Code Detected Condition (LUP). Set when the loop up code as defined in the RUPCD1 and
RUPCD2 re
gisters is being received.
Register Name:
RRTS3-E1
Register Description:
Receive Real-Time Status Register 3 (E1 Mode)
Register Address:
base address + 0x2C8
Bit # 7 6 5 4 3 2 1 0
Name - - - - LORC - V52LNK RDMA
Default 0 0 0 0 0 0 0 0
Note: This register has an alternate definition for E1 mode. See RRTS3-T1.
These bits p
rovide real-time status information from the receive framer.
Bit 3: Loss of Receive Clock Condition (LORC). Set when the RCLK pin has not transitioned for one channel
time.
Bit 1: V5.2 Link Detected Condition (V52LNK). Set on detection of a V5.2 link identification signal. (G.965).
Bit 0: Receive Distant MF Alarm Condition (RDMA). Set when bit 6 of timeslot 16 in frame 0 has been set for
two consecutive multiframes. This alarm is not disabled in the CCS signaling mode.