Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
RIM7-E1
Register Description:
Receive Interrupt Mask Register 7 (E1 Mode)
Register Address:
base address + 0x298
Bit # 7 6 5 4 3 2 1 0
Name - - - - - - Sa6CD SaXCD
Default 0 0 0 0 0 0 0 0
Note: This register has an alternate definition for E1 mode. See RIM7-T1.
The bits in th
e register are interrupt mask/enable bits for corresponding latched status bits in RLS7-E1.
Bit 1: Sa
6 Codeword Detect (Sa6CD).
0 = interrupt masked
1 = interrupt enabled
Bit 0: SaX Bit Change Detect (SaXCD).
0 = interrupt masked
1 = interrupt enabled
Register Name:
RSCSE1, RSCSE2, RSCSE3, RSCSE4
Register Description:
Receive Signaling Change of State Enable
Register Address:
base address + 0x2A0, 0x2A4, 0x2A8, 0x2AC
Bit # 7 6 5 4 3 2 1 0
RSCSE1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
RSCSE2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
RSCSE3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
RSCSE4 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
Bits 7 to 0 (x3): Receive Signaling Change of State Interrupt Enable for Channels 1 to 32 (CH1 to CH32). The
bits in these registers are interrupt enables for the corresponding bits in the RSS1 throug
h RSS4 registers. When a
channel’s signaling data changes state, the latched status bit for that channel in the RSS1 throu
gh RSS4 registers
is set to 1. The RLS4.RS
COS latched status bit is also set if the channel is enabled by the corresponding bit in
these RSCSE regi
sters. The setting of RLS4.RSCOS generates an interrupt request if enabled by RIM4.RSCOS.
See Section 10.11.3.2.
Register Name:
RUPCD1
Register Description:
Receive Up Code Definition Register 1
Register Address:
base address + 0x2B0
Bit # 7 6 5 4 3 2 1 0
Name C7 C6 C5 C4 C3 C2 C1 C0
Default 0 0 0 0 0 0 0 0
Note: Writing this register resets the detector’s integration period. See Section 10.11.14.
Bit 7:
Receive Up Code Definition Bit 7 (C7). First bit of the repeating pattern.
Bit 6: Receive Up Code Definition Bit 6 (C6). Ignored if a 1-bit length is selected.
Bit 5: Receive Up Code Definition Bit 5 (C5). Ignored if a 1 or 2 bit length is selected.
Bit 4: Receive Up Code Definition Bit 4 (C4). Ignored if a 1 to 3 bit length is selected.