Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Bit 3: Receive Packet End Event (RPE).
0 = interrupt masked
1 = interrupt enabled
Bit 2: Receive Packet Start Event (RPS).
0 = interrupt masked
1 = interrupt enabled
Bit 1: Receive FIFO Above High Watermark Set Event (RHWMS).
0 = interrupt masked
1 = interrupt enabled
Bit 0: Receive FIFO Not Empty Set Event (RNES).
0 = interrupt masked
1 = interrupt enabled
Register Name:
RIM7-T1
Register Description:
Receive Interrupt Mask Register 7 (T1 Mode)
Register Address:
base address + 0x298
Bit # 7 6 5 4 3 2 1 0
Name - - RRAI-CI RAIS-CI RSLC96 RFDLF BC BD
Default 0 0 0 0 0 0 0 0
Note: This register has an alternate definition for E1 mode. See RIM7-E1.
The bits in th
e register are interrupt mask/enable bits for corresponding latched status bits in RLS7-T1.
Bit 5:
Receive RAI-CI Detect (RRAI-CI).
0 = interrupt masked
1 = interrupt enabled
Bit 4: Receive AIS-CI Detect (RAIS-CI).
0 = interrupt masked
1 = interrupt enabled
Bit 3: Receive SLC-96 Alignment Event (RSLC96).
0 = interrupt masked
1 = interrupt enabled
Bit 2: Receive FDL Register Full Event (RFDLF).
0 = interrupt masked
1 = interrupt enabled
Bit 1: BOC Clear Event (BC).
0 = interrupt masked
1 = interrupt enabled
Bit 0: BOC Detect Event (BD).
0 = interrupt masked
1 = interrupt enabled