Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
RIM4
Register Description:
Receive Interrupt Mask Register 4
Register Address:
base address + 0x28C
Bit # 7 6 5 4 3 2 1 0
Name RESF RESEM RSLIP - RSCOS 1SEC TIMER RMF
Default 0 0 0 0 0 0 0 0
The bits in the register are interrupt mask/enable bits for corresponding latched status bits in RLS4.
Bit 7:
Receive Elastic Store Full Event (RESF).
0 = interrupt masked
1 = interrupt enabled
Bit 6: Receive Elastic Store Empty Event (RESEM).
0 = interrupt masked
1 = interrupt enabled
Bit 5: Receive Elastic Store Slip Occurrence Event (RSLIP).
0 = interrupt masked
1 = interrupt enabled
Bit 3: Receive Signaling Change Of State Event (RSCOS).
0 = interrupt masked
1 = interrupt enabled
Bit 2: One Second Timer (1SEC).
0 = interrupt masked
1 = interrupt enabled
Bit 1: Timer Event (TIMER).
0 = interrupt masked
1 = interrupt enabled
Bit 0: Receive Multiframe Event (RMF).
0 = interrupt masked
1 = interrupt enabled
Register Name:
RIM5
Register Description:
Receive Interrupt Mask 5 (HDLC)
Register Address:
base address + 0x290
Bit # 7 6 5 4 3 2 1 0
Name - - ROVR RHOBT RPE RPS RHWMS RNES
Default 0 0 0 0 0 0 0 0
The bits in the register are interrupt mask/enable bits for corresponding latched status bits in RLS5.
Bit 5:
Receive FIFO Overrun (ROVR).
0 = interrupt masked
1 = interrupt enabled
Bit 4: Receive HDLC Opening Byte Event (RHOBT).
0 = interrupt masked
1 = interrupt enabled