Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
RIM2
Register Description:
Receive Interrupt Mask Register 2 (E1 Mode Only)
Register Address:
base address + 0x284
Bit # 7 6 5 4 3 2 1 0
Name - - - - RSA1 RSA0 RCMF RAF
Default 0 0 0 0 0 0 0 0
The bits in the register are interrupt mask/enable bits for corresponding latched status bits in RLS2-E1.
Bit 3:
Receive Signaling All Ones Event (RSA1).
0 = interrupt masked
1 = interrupt enabled
Bit 2: Receive Signaling All Zeros Event (RSA0).
0 = interrupt masked
1 = interrupt enabled
Bit 1: Receive CRC-4 Multiframe Event (RCMF).
0 = interrupt masked
1 = interrupt enabled
Bit 0: Receive Align Frame Event (RAF).
0 = interrupt masked
1 = interrupt enabled
Register Name:
RIM3-T1
Register Description:
Receive Interrupt Mask Register 3 (T1 Mode)
Register Address:
base address + 0x288
Bit # 7 6 5 4 3 2 1 0
Name LORCC LSPC LDNC LUPC LORCD LSPD LDND LUPD
Default 0 0 0 0 0 0 0 0
Note: This register has an alternate definition for E1 mode. See RIM3-E1.
The bits in th
e register are interrupt mask/enable bits for corresponding latched status bits in RLS3-T1.
Bit 7: Lo
ss of Receive Clock Condition Clear (LORCC).
0 = interrupt masked
1 = interrupt enabled
Bit 6: Spare Code Detected Condition Clear (LSPC).
0 = interrupt masked
1 = interrupt enabled
Bit 5: Loop Down Code Detected Condition Clear (LDNC).
0 = interrupt masked
1 = interrupt enabled
Bit 4: Loop Up Code Detected Condition Clear (LUPC).
0 = interrupt masked
1 = interrupt enabled
Bit 3: Loss of Receive Clock Condition Detect (LORCD).
0 = interrupt masked
1 = interrupt enabled