Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
RLS7-T1
Register Description:
Receive Latched Status Register 7 (T1 Mode)
Register Address:
base address + 0x258
Bit # 7 6 5 4 3 2 1 0
Name - - RRAI-CI RAIS-CI RSLC96 RFDLF BC BD
Default 0 0 0 0 0 0 0 0
Note: This register has an alternate definition for E1 mode. See RLS3-E1.
Bit 5
: Receive RAI-CI Detect (RRAI-CI). This latched status bit is set when an RAI-CI pattern has been detected
by the receiver. This bit is active in ESF framing mode only, and sets only if an RAI condition is being detected
(RRTS1.R
RAI=1). RRAI-CI is cleared when written with a 1. When RRAI-CI is set it can cause an interrupt request
if the corresponding interrupt enable bit is set in the RIM7-T1 regi
ster. See Section 10.11.6.4.
Bit
4: Receive AIS-CI Detect (RAIS-CI). This latched status bit is set when an AIS-CI pattern has been detected
by the receiver. This bit is set only if an AIS condition is being detected (RRTS1.RAIS=1). RRAI-CI is
cleared when
written with a 1. When RAIS-CI is set it can cause an interrupt request if the corresponding interrupt enable bit is
set in the RIM7-T1re
gister. See Section 10.11.6.4.
Bit 3
: Receive SLC-96 Alignment Event (RSLC96). This latched status bit is set when a valid SLC-96 alignment
pattern is detected in the Fs bit stream, and the RSLC regi
sters have data available for retrieval.. RSLC96 is
cleared when written with a 1. When RSLC96 is set it can cause an interrupt request if the corresponding interrupt
enable bit is set in the RIM7-T1 regi
ster. See section 10.11.16.
Bit 2
: Receive FDL Register Full Event (RFDLF). This latched status bit is set when the RFDL regi
ster is full.
Useful for SLC-96 operation, or manual extraction of FDL data bits. RFDLF is cleared when written with a 1. When
RFDLF is set it can cause an interrupt request if the corresponding interrupt enable bit is set in the RIM7-T1
regi
ster. See Section 10.11.4.4.
Bit 1: BOC Clear Event (BC). This latched status bit is set when a valid BOC is no longer detected (with the
RBOCC.RB
D disintegration filter applied). BC is cleared when written with a 1. When BC is set it can cause an
interrupt request if the corresponding interrupt enable bit is set in the RIM7-T1 re
gister. See section 10.11.4.2.
Bit 0
: BOC Detect Event (BD). This latched status bit is set when a valid BOC has been detected (with the
RBOCC.RB
F filter applied). BD is cleared when written with a 1. When BD is set it can cause an interrupt request if
the corresponding interrupt enable bit is set in the RIM7-T1 regi
ster. See section 10.11.4.2.
Register Name:
RLS7-E1
Register Description:
Receive Latched Status Register 7 (E1 Mode)
Register Address:
base address + 0x258
Bit # 7 6 5 4 3 2 1 0
Name - - - - - - Sa6CD SaXCD
Default 0 0 0 0 0 0 0 0
Note: This register has an alternate definition for E1 mode. See RLS7-T1.
Bit 1: Sa6 Codeword Detect (Sa6CD). This latched status bit is set when a valid codeword (per ETS 300 233) is
detected in the Sa6 bit position. Sa6CD is cleared when written with a 1. When Sa6CD is set it can cause an
interrupt request if the corresponding interrupt enable bit is set in the RIM7-E1 re
gister. See section 10.11.5.3.
Bit 0: SaX Bi
t Change Detect (SaXCD). This latched status bit is set when the value of a received Sa bit changes
and interrupts are enabled for that Sa bit in the RSAIMR regi
ster. SaXCD is cleared when written with a 1. When
SaXCD is set it can cause an interrupt request if the corresponding interrupt enable bit is set in the RIM7-E1
regi
ster. See section 10.11.5.3.