Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
RLS3-E1
Register Description:
Receive Latched Status Register 3 (E1 Mode)
Register Address:
base address + 0x248
Bit # 7 6 5 4 3 2 1 0
Name LORCC - V52LNKC RDMAC LORCD - V52LNKD RDMAD
Default 0 0 0 0 0 0 0 0
Note: This register has an alternate definition for E1 mode. See RLS3-T1.
Bit 7
: Loss of Receive Clock Clear (LORCC). This latched status bit is set to 1 when RRTS3-E1.LO
RC changes
state from high to low. LORCC is cleared when written with a 1. When LORCC is set it can cause an interrupt
request if the LORCC interrupt enable bit is set in the RIM3-E1 regi
ster.
Bit 5: V5.2 Link Detected Clear (V52LNKC). This latched status bit is set to 1 when RRTS3-E1.V52L
NK changes
state from high to low. V52LNKC is cleared when written with a 1. When V52LNKC is set it can cause an interrupt
request if the V52LNKC interrupt enable bit is set in the RIM3-E1 re
gister.
Bit 4: Receive Distant MF Alarm Clear (RDMAC). This latched status bit is set to 1 when RRTS3-E1.RDMA
changes state from high to low. RDMAC is cleared when written with a 1. When RDMAC is set it can cause an
interrupt request if the RDMAC interrupt enable bit is set in the RIM3-E1 regi
ster.
Bit 3: Loss of Receive Clock Detect (LORCD). This latched status bit is set to 1 when RRTS3-E1.LO
RC changes
state from low to high. LORCD is cleared when written with a 1. When LORCD is set it can cause an interrupt
request if the LORCD interrupt enable bit is set in the RIM3-E1 regi
ster.
Bit 1: V5.2 Link Detect (V52LNKD). This latched status bit is set to 1 when RRTS3-E1.
V52LNK changes state
from low to high. V52LNKD is cleared when written with a 1. When V52LNKD is set it can cause an interrupt
request if the V52LNKD interrupt enable bit is set in the RIM3-E1 re
gister.
Bit 0: Receive Distant MF Alarm Detect (RDMAD). This latched status bit is set to 1 when RRTS3-E1.RDMA
changes state from low to high. RDMAD is cleared when written with a 1. When RDMAD is set it can cause an
interrupt request if the RDMAD interrupt enable bit is set in the RIM3-E1 regi
ster.
Register Name:
RLS4
Register Description:
Receive Latched Status Register 4
Register Address:
base address + 0x24C
Bit # 7 6 5 4 3 2 1 0
Name RESF RESEM RSLIP - RSCOS 1SEC TIMER RMF
Default 0 0 0 0 0 0 0 0
Bit 7: Receive Elastic Store Full Event (RESF). This latched status bit is set to 1 when the receive elastic store
buffer fills and a frame is deleted. RESF is cleared when written with a 1. When RESF is set it can cause an
interrupt request if the corresponding interrupt enable bit is set in the RIM4 re
gister. See Section 10.10.
Bit
6: Receive Elastic Store Empty Event (RESEM). This latched status bit is set to 1 when the receive elastic
store buffer empties and a frame is repeated. RESEM is cleared when written with a 1. When RESEM is set it can
cause an interrupt request if the corresponding interrupt enable bit is set in the RIM4 regi
ster. See Section 10.10.
Bit 5
: Receive Elastic Store Slip Occurrence Event (RSLIP). This latched status bit is set to 1 when the receive
elastic store has either repeated or deleted a frame (i.e. either RESF or RESEM set). RSLIP is cleared when
written with a 1. When RSLIP is set it can cause an interrupt request if the corresponding interrupt enable bit is set
in the RIM4 registe
r. See Section 10.10.
Bit 3
: Receive Signaling Change Of State Event (RSCOS). This latched status bit is set to 1 when any channel
selected by the Receive Signaling Change Of State Interrupt Enable registers (RSCSE1 throu
gh RSCSE4),