Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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0 = MECU bit is used to manually update error counter registers
1 = GCR1.G
FCLE is used to manually update error counter registers
Bit 5: Manual Error Counter Update (MECU). When enabled by EAMS=1, changing this bit from zero to one
allows the next clock cycle to load the error counter registers with the latest counts and reset the counters. The
CPU must wait a minimum of 250
s before reading the error count registers to allow for proper update. See section
10.11.8.
Bit 4: Erro
r Counter Update Select (ECUS). This field is ignored when EAMS=1. See section 10.11.8.
T1 mode:
0 = Up
date error counter registers once each second
1 = Update error counter registers every 42ms (333 frames)
E1 mode:
0 = Update error counter registers once a second
1 = Update error counter registers every 62.5ms (500 frames)
Bit 3: Error Accumulation Mode Select (EAMS). See section 10.11.8.
0 =
Automatic update of error counter registers. The ECUS bit determines update interval.
1 = The CPU toggles the MECU bit (per-framer manual update) when MCUS=0 or the GCR1.G
FCLE bit
(global manual update) when MCUS=1 determines the update times.
Bit 2: PCVCR Fs-Bit Error Report Enable (FSBE). T1 Mode Only. See section 10.11.8.2.
0 = do not re
port bit errors in Fs bit positions; only Ft bit positions
1 = report bit errors in Fs bit positions as well as Ft bit positions
Bit 1: Multiframe Out-of -Sync Count Register Function Select (MOSCRF). T1 Mode Only. See section
10.11.8.3.
0 = co
unt errors in the framing bit position
1 = count the number of multiframes out of sync
Bit 0: Line Code Violation Count Register Function Select (LCVCRF). See section 10.11.8.1.
T1 mode:
0 = do not co
unt excessive zeros
1 = count excessive zeros
E1 mode:
0 = count BPVs
1 = count code violations (CVs)
Register Name:
RHFC
Register Description:
Receive HDLC FIFO Control Register
Register Address:
base address + 0x21C
Bit # 7 6 5 4 3 2 1 0
Name - - - - - - RFHWM1 RFHWM0
Default 0 0 0 0 0 0 0 0
Bits 1 to 0: Receive FIFO High Watermark Select (RFHWM[1:0]). See section 10.12.1
RFH
WM1 RFHWM0 Receive FIFO Watermark
0 0 4 bytes
0 1 16 bytes
1 0 32 bytes
1 1 48 bytes