Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
25 of 366
8
Overview of Major Operational Modes
8.1
Internal Mode
The default mode of the device is internal one-clock mode. Internal mode is used to internally connect the framers
to the TDMoP block. Internal mode additionally configures many unused TDM interface output pins to drive low.
Unused TDM interface input pins are ignored. Figure 8-1 sho
ws an internal mode version of the Figure 6-1 block
diagram with wires to unused inputs and outputs shown in a grey color. All ports of the device are configured in
internal mode when GCR1.
MODE=0. When GCR1.MODE=1, all ports are configured in external mode by default,
but (DS34T108 only) individual ports can be configured for internal mode using the GCR1.INTMODE
n bits. Figure
6-2 shows how the device is internally connected inside the TDM cross-connect block in internal mode.
Figure 8-1. Internal Mode Block Diagram
LIU
Transmitter
Waveshape,
Line Driver
LIU
Receiver
Clock and Data
Recovery
Rx
BERT
Rx Framer
Rx
HDLC
TDMoP Block
all 8 ports
Clock
Recovery
Machines
Timeslot
Assigner
CAS
Handler
SDRAM
Controller
Jitter
Buffer
Control
Queue
Manager
Ethernet
MAC
10/100
Packet
Classifier
Counters
& Status
Registers
CPU
Interface
SD_D[31:0]
SD_DQM[3:0]
SD_A[11:0]
SD_BA[1:0]
SD_CLK
SD_CS_N
SD_WE_N
SD_RAS_N
SD_CAS_N
CLK_MII_RX
MII_RXD[3:0]
MII_RX_DV
MII_RX_ERR
MII_COL
MII_CRS
CLK_MII_TX
CLK_SSMII_TX
MII_TXD[3:0]
MII_TX_EN
MDIO
MDC
CLK_SYS
CLK_HIGH
RST_SYS_N
JTAG
JTMS
JTCLK
JTDI
JTDO
JTRST_EN
TTIPn
TRINGn
RTIPn
RRINGn
LIU & Framer (1 of 8)
MCLK
TXENABLE
RXTSEL
RESREF
TCLKOn
MII_TX_ERR
CLAD1
38.88MHz
2.048/1.544MHz
CLAD2
50 or 75MHz
CLK_SYS_S
CLK_CMN
SCEN
SCAN
MBIST
STMD
MBIST_EN
MBIST_DONE
MBIST_FAIL
HIZ_EN
E1CLK
T1CLK
B8ZS/HDB3
Decoder
E1CLK
T1CLK
RCLKn (out)/RCLKFn (in)
RDATFn
Rx Elastic Store
TDATFn
B8ZS/HDB3
Encoder
Tx Formatter
Tx Elastic Store
Tx
BERT
Tx
HDLC
FSYSCLK
Jitter Attenuator
RLOFn/RLOSn
E1CLK
T1CLK
FSYSCLK
clk
clkneg
neg pos/dat
0101
LIUDn
LIUDn
LIUDn
clkneg
pos/dat
pos/dat
clkneg pos/dat
RCLK
RSIG
888
1 of 8 ports
all 8 ports
888
TDM Cross-Connection
and External Interfaces
888
RF/MSYNC
8
8
TCLK
TSIG
TSER (data)
T(S)SYNC in
8
88
Control
Bank Select
Address
Byte Enable Mask
Data
RCLK
RSIG_RTS
RX (data)
RX_SYNC
TCLK
TSIG_CTS
TX (data)
TX_SYNC
88
8
RSYSCLK
TSYNC out
8
8
RSYNC in
8
TSYSCLK
E1CLK
T1CLK
RSER
(data)
RCLK
8
RSYNC out
8
8
H_D[31:1]
H_AD[24:1]
H_CS_N
H_R_W_N
H_WR_BE[0]_N / SPI_CLK
H_READY_N
H_INT[1:0]
DATA_31_16_N
H_CPU_SPI_N
H_D[0] / SPI_MISO
H_WR_BE[1]_N / SPI_MOSI
H_WR_BE[2]_N / SPI_SEL_N
H_WR_BE[3]_N / SPI_CI
Payload Type
Machines
AAL1
HDLC
SAToP
CESoPSN
RAW