Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
RCR3
Register Description:
Receive Control Register 3
Register Address:
base address + 0x20C
Bit # 7 6 5 4 3 2 1 0
Name IDF uALAW RSERC BINV1 BINV0 - PLB FLB
Default 0 0 0 0 0 0 0 0
Bit 7: Input Data Format (IDF). See the pos/dat and neg signals in the Rx path in Figure 6-1.
0 =
Bipolar data (AMI, HDB3 or B8ZS format) is expected from the LIU on the pos and neg signals.
1 = NRZ data is expected from the LIU pos/dat signal or from the RDATFn pin. The B
PV counter is
disabled and the neg signal is ignored.
Bit 6: u-Law or A-Law Digital Milliwatt Code Select (uALAW)
0 = u-law code is inserted based on the RDMWE regi
sters.
1 = A-law code is inserted based on the RDMWE regi
sters.
Bit 5: RSER Control (RSERC). See the RSER signal in the Rx path in Figure 6-1.
0 = allo
w RSER to output data as received under all conditions (normal operation)
1 = force RSER to one under loss-of-frame-alignment conditions
Bits 4 to 3: Rx Bit Inversion (BINV[1:0])
00 = No inversion
01 = Invert framing
10 = Invert signaling
11 = Invert payload
Bit 1: Payload Loopback (PLB).
0 = loopback disabled
1 = loopback enabled
Bit 0: Framer Loopback (FLB).
0 = loopback disabled
1 = loopback enabled