Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
RNAF
Register Description:
Receive Non-Align Frame Register (E1 Mode)
Register Address:
base address + 0x194
Bit # 7 6 5 4 3 2 1 0
Name Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8
Default 0 0 0 0 0 0 0 0
Note: This register has an alternate definition for T1 mode. See RSLC2.
The no
n-align frame is the E1 frame that does not contain the frame alignment signal (FAS). The bits of this
register indicate the first eight bits received in the most recent non-align frame. The bits are latched into this
register at the start of the align frame. The start of the align frame is indicated by the RAF status bit in RLS2-E1.
See Section 10.11.5.1.
Bit 7: International Bit (Si
).
Bit 6: Non-Align Frame Signal Bit. Set to 1 in a normal E1 double frame.
Bit 5: Remote Alarm Indication (RAI). This is the normal status bit for detecting RAI in the incoming E1 signal.
0 = No alarm condition
1 = Alarm condition
Bits 4 to 0: Additional Spare Bits (Sa4 to Sa8).
Register Name:
RSiAF
Register Description:
Receive Si bits of the Align Frame (E1 Mode)
Register Address:
base address + 0x198
Bit # 7 6 5 4 3 2 1 0
Name SiF14 SiF12 SiF10 SiF8 SiF6 SiF4 SiF2 SiF0
Default 0 0 0 0 0 0 0 0
Note: This register has an alternate definition for T1 mode. See RSLC3.
The ali
gn frame is the E1 frame containing the frame alignment signal (FAS). The bits of this register indicate the Si
bits received in the align frames of the most recent CRC-4 multiframe. The Si bits received in each multiframe are
saved in internal registers and latched into this register at the start of the next CRC-4 multiframe. The CRC-4
multiframe boundary is indicated by the RCMF status bit in RLS2-E1. See Sectio
n 10.11.5.2.
Bit 7: Si Bit of Frame 14 (SiF14).
Bit 6: Si Bit of Frame 12 (SiF12).
Bit 5: Si Bit of Frame 10 (SiF10).
Bit 4: Si Bit of Frame 8 (SiF8).
Bit 3: Si Bit of Frame 6 (SiF6).
Bit 2: Si Bit of Frame 4 (SiF4).
Bit 1: Si Bit of Frame 2 (SiF2).
Bit 0: Si Bit of Frame 0 (SiF0).