Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
RDS0M
Register Description:
Receive DS0 Monitor Register
Register Address:
base address + 0x180
Bit # 7 6 5 4 3 2 1 0
Name B1 B2 B3 B4 B5 B6 B7 B8
Default 0 0 0 0 0 0 0 0
Bits 7 to 0: Rx DS0 Channel Bits (B1 to B8). Rx data for the channel specified by the Rx DS0 Monitor Select
Register, RDS0SEL. B8 is the LSb of the DS0 ch
annel (last bit to be received). See section 10.11.9.
Register Name:
REVID
Register Description:
Framer Revision ID Register
Register Address:
base address + 0x184
Bit # 7 6 5 4 3 2 1 0
Name REVID7 REVID6 REVID5 REVID4 REVID3 REVID2 REVID1 REVID0
Default 0 0 0 0 0 0 1 1
Bits 7 to 0: Revision ID (REVID[7:0]). This read-only register reports the current framer revision.
Register Name:
RFDL
Register Description:
Receive FDL Register (T1 Mode Only)
Register Address:
base address + 0x188
Bit # 7 6 5 4 3 2 1 0
Name RFDL7 RFDL6 RFDL5 RFDL4 RFDL3 RFDL2 RFDL1 RFDL0
Default 0 0 0 0 0 0 0 0
Note: This register has an alternate definition for E1 mode. See RRTS7.
Bits 7 to 0: Rx FDL (RFDL[7:0]). This register reports the last byte received in the facilities data link. Bit 7 is the
MSb. See section 10.11.4.4.
Register Name:
RRTS7
Register Description:
Receive Real-Time Status Register 7 (E1 Mode Only)
Register Address:
base address + 0x188
Bit # 7 6 5 4 3 2 1 0
Name CSC5 CSC4 CSC3 CSC2 CSC0 CRC4SA CASSA FASSA
Default 0 0 0 0 0 0 0 0
Note: This register has an alternate definition for T1 mode. See RFDL. All bits in this register are read-only real-
time status (not latched).
Bits 7 to 3: CRC-4 Sync Counter (CSC[5:2] and CSC0). The CRC-4 sync counter increments each time the 8 ms
CRC-4 multiframe search times out. The counter is cleared when the framer has successfully obtained
synchronization at the CRC-4 level. The counter can also be cleared by disabling the CRC-4 mode (RCR1-
E1.RC
RC4=0). This counter is useful for determining the amount of time the framer has been searching for
synchronization at the CRC-4 level. ITU-T G.706 suggests that if synchronization at the CRC-4 level cannot be
obtained within 400 ms, then the search should be abandoned and proper action taken. The CRC-4 sync counter
saturates (does not rollover). CSC0 is the LSB of the 6–bit counter. (Note: The next to LSB is not accessible. CSC1
is omitted to allow resolution to >400ms using 5 bits.)