Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
RBOCC
Register Description:
Receive BOC Control Register (T1 Mode Only)
Register Address:
base address + 0x054
Bit # 7 6 5 4 3 2 1 0
Name RBR - RBD1 RBD0 RIE RBF1 RBF0 -
Default 0 0 0 0 0 0 0 0
Bit 7: Rx BOC Reset (RBR). Setting this bit to 1 forces a reset of the BOC circuitry. Note that this is an
acknowledged reset – the CPU sets the bit and the device clears it after the reset operation is complete (less than
250
s). Modifications to the RBF[1:0] and RBD[1:0] fields are ignored by the BOC controller until a BOC reset has
been completed. See section 10.11.4.2.
Bits
5, 4: Rx BOC Disintegration (RBD[1:0]). The BOC disintegration filter sets the number of message bits that
must be received without a valid BOC before the RLS7.BC bit i
s set to indicate that a valid BOC is no longer being
received. See section 10.11.4.2.
RB
D1 RBD0
CONSECUTIVE MESSAGE BITS
FOR BOC CLEAR IDENTIFICATION
0 0 16
0 1 32
1 0 48
1 1 64
1
Bit 3: RBOC 7/10 Integration Enable (RBI). This bit enables RBOC 7 of 10 integration. See section 10.11.4.2.
0 = 7/10 integration disable
1 = 7/10 integration enabled
Bits 2, 1: Rx BOC Filter bits (RBF[1:0]). The BOC filter sets the number of consecutive BOC codes that must be
received without error before the RLS7-T1.BD bit i
s set to indicate that a valid BOC is being received. See section
10.11.4.2.
RBF
1 RBF0
CONSECUTIVE BOC CODES FOR
VALID SEQUENCE IDENTIFICATION
0 0 None
0 1 3
1 0 5
1 1 7
1
Note 1. The BOC controller does not integrate and disintegrate concurrently. Therefore, if the maximum integration
and disintegration times are taken together, BOC messages that repeat fewer than 11 times may not be detected.
Register Name:
RIDR1 to RIDR32
Register Description:
Receive Idle Code Definition Registers 1 to 32
Register Address:
base address + 0x080 + 0x04*(n-1), n = channel number = 1 to 32
Bit # 7 6 5 4 3 2 1 0
Name C7 C6 C5 C4 C3 C2 C1 C0
Default 0 0 0 0 0 0 0 0
Bits 7 to 0: Per-Channel Idle Code Bits (C[7:0]). C0 is the LSB of the code (this bit is transmitted last). Address
0x80 holds the idle code for channel 1. Address 0xDC is for channel 24. Address 0xFC is for channel 32. Note that
RIDR25 to RIDR32 are only for E1 mode and become the RSAOI and RDMWE regi
sters in T1 mode. See section
10.11.12.