Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Bit 1: Rx RAI Integration Enable (RAIIE). The ESF RAI indication can be interrupted for a period not to exceed
100ms per interruption (T1.403). In ESF mode, setting RAIIE causes the RAI status from the framer to be
integrated for 200ms.
0 = RAI detects when 16 consecutive patterns of 0x00FF appear in the FDL. RAI clears when 14 or less
patterns of 0x00FF out of 16 possible appear in the FDL
1 = RAI detects when the condition has been present for greater than 200ms. RAI clears when the
condition has been absent for greater than 200ms.
Bit 0: Rx Side D4 Remote Alarm Select (RD4RM).
0 = zeros in bit 2 of all channels
1 = a one in the S-bit position of frame 12 (Japanese J1 yellow alarm mode)
Register Name:
RSAIMR
Register Description:
Receive Sa Bit Interrupt Mask Register (E1 Mode)
Register Address:
base address + 0x050
Bit # 7 6 5 4 3 2 1 0
Name - - - RSa4IM RSa5IM RSa6IM RSa7IM RSa8IM
Default 0 0 0 0 0 0 0 0
Note: This register has an alternate definition for T1 mode. See RCR2-T1.
See se
ction 10.11.5.3.
Bit 4: Sa
4 Change Detect Interrupt Mask. This bit enables the change detect interrupt for the Sa4 bit. Any
change of state of the received Sa4 bit generates an interrupt (RLS7.SaXCD
) to indicate the change of state.
0 = Interrupt Masked.
1 = Interrupt Enabled
Bit 3: Sa5 Change Detect Interrupt Mask. This bit enables the change detect interrupt for the Sa5 bit. Any
change of state of the received Sa5 bit generates an interrupt (RLS7-E1.SaXC
D) to indicate the change of state.
0 = Interrupt Masked.
1 = Interrupt Enabled.
Bit 2: Sa6 Change Detect Interrupt Mask. This bit enables the change detect interrupt for the Sa6 bit. Any
change of state of the received Sa6 bit generates an interrupt (RLS7-E1.SaXC
D) to indicate the change of state.
0 = Interrupt Masked.
1 = Interrupt Enabled.
Bit 1: Sa7 Change Detect Interrupt Mask. This bit enables the change detect interrupt for the Sa7 bit. Any
change of state of the received Sa7 bit generates an interrupt (RLS7-E1.SaXC
D) to indicate the change of state.
0 = Interrupt Masked.
1 = Interrupt Enabled.
Bit 0: Sa8 Change Detect Interrupt Mask. This bit enables the change detect interrupt for the Sa8 bit. Any
change of state of the received Sa8 bit generates an interrupt (RLS7-E1.SaXC
D) to indicate the change of state.
0 = Interrupt Masked.
1 = Interrupt Enabled.