Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108

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Bit 6: Receive HDLC Reset (RHR). Resets the receive HDLC controller and flushes the receive HDLC FIFO. Note

that this bit is an acknowledged reset. The CPU sets this bit and the device clears it after the reset operation is

complete. The device completes the HDLC reset within 2 frames. See section 10.12.1.

0 = No

rmal operation

1 = Reset receive HDLC controller and flush the Rx HDLC FIFO

Bit 5: Receive HDLC Mapping Select (RHMS). See section 10.12.1.

0 = Re

ceive HDLC assigned to DS0 channel specified by RHCS[4:0] below

1 = Receive HDLC assigned to FDL (T1 mode) or Sa Bits (E1 mode)

Bit 4 to 0: Receive HDLC Channel Select 4 to 0 (RHCS[4:0]). These bits specify which DS0 is mapped to the

HDLC controller when enabled with RHMS=0. RHCS[4:0]=00000 selects channel 1, while RHCS[4:0]=11111

selects channel 32. Channel numbers greater than 24 are invalid in T1 mode. A change to this field is

acknowledged only after a receive HDLC reset (RHR bit above). See section 10.12.1.

RHBSE

Receive HDLC Bit Suppress Register

base address + 0x044

Bit # 7 6 5 4 3 2 1 0

Name BSE8 BSE7 BSE6 BSE5 BSE4 BSE3 BSE2 BSE1

Default 0 0 0 0 0 0 0 0

Bits 7 to 0: Rx Bit Suppress 8 to 1 (BSE[8:1]). These bits specify whether the corresponding bit of the DS0

channel should be included or excluded (suppressed) in the data stream sent to the Rx HDLC controller. BSE8 is

the MSb of the channel. See section 10.12.1.

0 = Include this bit in the data stream

1= Don’t include (suppress) this bit

RDS0SEL

Receive DS0 Monitor Select Register

base address + 0x048

Bit # 7 6 5 4 3 2 1 0

Name - - - RCM4 RCM3 RCM2 RCM1 RCM0

Default 0 0 0 0 0 0 0 0

Bits 4 to 0: Rx Channel Monitor Bits (RCM[4:0]). This field specifies which Rx DS0 channel’s data is available to

be read from the RDS0M registe

r. 00000=channel 1. 11111=channel 32. See section 10.11.9.