Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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SQE_test_errors 0x084
Bits Data Element Name R/W
Reset
Value
Description
[31:8] Reserved - 0x0 Must be set to zero
[7:0] SQE_test_errors R/W 0x0 An 8-bit register counting the number of packets where
collision was not asserted within 96 bit times (an
interpacket gap) of MII_TX_EN being deasserted in half
duplex mode.
Transmitted_pause_packets 0x08C
Bits Data Element Name R/W
Reset
Value
Description
[31:16] Reserved - 0x0 Must be set to zero
[15:0] Transmitted_pause_packets R/W 0x0 A 16-bit register counting the number of pause packets
transmitted.