Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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MAC_network_control 0x000
Bits Data Element Name R/W
Reset
Value
Description
[3] Transmit_enable R/W 0x0 0 = Stop transmission immediately, clear the transmit
FIFO and control registers, and reset the transmit
queue pointer register to point to the start of the
transmit descriptor list.
1 = Enable the MAC transmitter to send data.
This bit must be set during normal operation.
[2] Rx_enable R/W 0x0 0 = Stop packet reception immediately
1 = Enable the MAC receiver to Rx data
[1:0] Reserved - 0x0 Must be set to zero
MAC_network_configuration 0x004
Bits Data Element Name R/W
Reset
Value
Description
[31:20] Reserved - 0x0 Read as zero, ignored on write
[19] Ignore_Rx_FCS R/W 0x0 When set, packets with FCS/CRC errors are not rejected
and no FCS error statistics are counted. For normal
operation, this bit must be set to 0.
[18] Enable_half_duplex_Rx R/W 0x0 Enable packets to be received in half-duplex mode while
transmitting.
[17] Reserved - 0x0 Must be set to zero
[16] Rx_length_field_checking_enabl
e
R/W 0x0 When set, packets with measured lengths shorter than
their length fields are discarded. Packets containing a
type ID in bytes 13 and 14 (length/type field ≥0600) are
not counted as length errors.
[15:14] Reserved - 0x0 Must be set to zero
[13] Pause_enable R/W 0x0 When set, Ethernet packet transmission pauses when a
valid pause packet is received.
[12] Retry_test R/W 0x0 Must be set to zero for normal operation. If set to one, the
back-off between collisions is always one slot time.
Setting this bit to one helps test the ‘too many retries
condition’. Also used in pause packet tests to reduce the
pause counters decrement time from 512 bit times to
every CLK_MII_RX cy
cle.
[11:10] MDC_frequency R/W 0x2 Set according to CLK_SYS speed. This field determines
by what number CLK_SYS is
divided to generate MDC.
For conformance with 802.3 MDC must not exceed 2.5
MHz. (MDC is only active during MDIO read and write
operations).
Must be set to 0x2.
[9] Reserved 0x0 Must be set to zero
[8] Rx_2000_byte_packets R/W 0x0 Setting this bit means the MAC receives packets up to
2000 bytes in length.
Normally the MAC rejects any packet above 1518 bytes
[7:5] Reserved 0x0 Must be set to zero
[4] Reserved R/W 0x0 Must be set to 1
[3:2] Reserved 0x0 Must be set to zero
[1] Full_duplex R/W 0x0 If set to 1 the transmit block ignores the state of collision
and carrier sense and allows Rx while transmitting.
[0] Speed R/W 0x0 0 = 10 Mbit/s operation
1 = 100 Mbit/s operation
Used only for RMII and SMII interfaces.