Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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11.4.16 Ethernet MAC
The base address for the Ethernet MAC register space is 0x72,000.
Configuration and status registers are listed in subsection 11.4.16.1. Counters a
re listed in subsection 11.4.16.2.
11.4.16.1 Ethernet MAC Configuration and Status Registers
Table 11-17. Ethernet MAC Registers
Addr
Offset
Register Name Description Page
0x00 3MAC_network_control MAC control register 214
0x04 3MAC_network_configuration MAC configuration register 215
0x08 3MAC_network_status MAC network status register 216
0x14 3MAC_transmit_status MAC transmitter status register 216
0x24 MAC_interrupt_status MAC interrupt status register 216
0x28 MAC_interrupt_enable MAC interrupt enable register 216
0x2C MAC_interrupt_disable MAC interrupt disable register 217
0x30 MAC_interrupt_mask MAC interrupt mask register 217
0x34 MAC_PHY_maintenance PHY maintenance register 218
0x38 MAC_pause_time MAC pause time register 218
0x98 MAC_specific_address_lower MAC specific address register (bits 31:0) 218
0x9C MAC_specific_address_upper MAC specific address register (bits 47:32) 218
0xBC 3MAC_transmit_paulse_quantum MAC transmit pause quantum register 219
0xC0 3PHY_SMII_status PHY SMII status register 219
When reading from Ethernet MAC data elements wider than 16 bits in 16-bit mode, use the following procedure:
1. Read from address 2, i.e. H_AD[1]
=1. All 32 bits are internally latched and bits 15:0 are output on
H_D[15:0].
2.
Read from address 0, i.e. H_AD [1]
=0. Bits 31:16 are output on H_D[15:0].
Whe
n writing to Ethernet MAC data elements wider than 16 bits in 16-bit mode, use the following procedure:
1. Write to address 2, i.e. H_AD[1]=1. Bits 15:0 are inte
rnally latched but not written to the register yet.
2. Write to address 0, i.e. H_AD [1]=0. All 32 bits are w
ritten to the register. Bits 31:16 on H_D[15:0] are
written to address 0. Bits 15:0 in the internal latch are written to address 2.
MAC_network_control 0x000
Bits Data Element Name R/W
Reset
Value
Description
[31:13] Reserved. RO 0x0 Read as zero, ignored on write
[12] Transmit_zero_quantum_pause_
packet
WO None Writing a 1 to this bit transmits a pause packet with zero
pause quantum at the next available transmitter idle time.
[11] Transmit_pause_packet WO None Writing 1 to this bit transmits a pause packet with the
pause quantum in the
3MAC_transmit_paulse_quantum
register — at the next available transmitter idle time.
[10:9] Reserved 0x0 Must be set to zero
[8] Back_pressure R/W 0x0 When set in half duplex mode forces collisions on all
received packets.
[7] Write_enable_for_statistics_
registers
R/W 0x0 Setting this bit to 1 makes the Ethernet MAC counter
registers writable for functional test purposes.
[6] Increment_statistics_reg WO 0x0 Writing 1 increments all statistics registers by one for test
purposes.
[5] Clear_statistics_reg WO 0x0 Writing 1 clears the statistics registers.
[4] Management_port_enable R/W 0x0 0 = Disable PHY management port (MDIO high
impedance, MDC forced low.)
1 = Enable the PHY management port