Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
212 of 366
CW_bits_mask_low_bundles 0x144
Bits Data Element Name R/W
Reset
Value
Description
CW_bits_change_low_bundles register.
CW_bits_change_high_bundles 0x148
Bits Data Element Name R/W
Reset
Value
Description
[31:0] CW_bits_change R/W 0xFFFF
FFFF
Bit 31 represents bundle 63 and bit 0 represents bundle
32. When a bit is set it indicates the corresponding bundle
had a change in one of the bundle’s control word fields: L,
R, M or FRG. The CW_bits_change_mask register
specifi
es which of the four Control Word fields can cause
an interrupt when changed. The current state of the four
fields can be read from the Packet Classifier Status
register i
n the per-bundle status tables (section 11.4.4.1).
CW_bits_mask_high_bundles 0x14C
Bits Data Element Name R/W
Reset
Value
Description
[31:0] CW_bits_mask R/W 0xFFFF
FFFF
Bit 31 represents bundle 63; bit 0 represents bundle 32.
Mask the interrupt from the corresponding bit in the
3CW_bits_change_high_bundles register.
CW_bits_change_mask 0x180
Bits Data Element Name R/W
Reset
Value
Description
[31:6] Reserved - 0x0 Must be set to zero
[5] Rx_sync_loss
R/W
None Mask interrupts caused by L field changing in Control
Word
[4] Rx_remote_fail
R/W
None Mask interrupts caused by R field changing in Control
Word
[3:2] Rx_Lbit_modifier
R/W
None Mask interrupts caused by M field changing in Control
Word
[1:0] Fragmentation_bits
R/W
None Mask interrupts caused by FRG field changing in Control
Word
CPU_Queues_change 0x1C0
Bits Data Element Name R/W
Reset
Value
Description
[31:10] Reserved - 0x0 Must be set to zero
[9] TDM_to_CPU_pool_thresh R/W 0x0
TDM to CPU pool level  threshold.
[8] TDM_to_CPU_q_thresh R/W 0x0
TDM to CPU queue level  threshold.
[7] CPU_to_ETH_q_thresh R/W 0x0
CPU to Ethernet queue level  threshold.
[6] ETH_to_CPU_pool_thresh R/W 0x0
Ethernet to CPU pool level  threshold.
[5] ETH_to_CPU_q_thresh R/W 0x0
Ethernet to CPU queue level  threshold
[4:3] Reserved R/W 0x0 Must be set to zero
[2] CPU_to_TDM_q_thresh R/W 0x0
CPU to TDM queue level  threshold.
[1] Tx_return_q_thresh R/W 0x0
CPU TX return queue level  threshold.
[0] Rx_return_q_thresh R/W 0x0
CPU RX return queue level  threshold.