Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Intmask 0x004
Bits Data Element Name R/W
Reset
Value
Description
[25] CW_Bits_change R/W 0x1 Mask Control Word bits change interrupt.
[24] RTS_changes R/W 0x1 Mask RTS change interrupt.
[23] Tx_CAS_change_P8 R/W 0x1 Mask Tx_CAS_change_P8 interrupt.
[22] Tx_CAS_change_P7 R/W 0x1 Mask Tx_CAS_change_P7 interrupt.
[21] Tx_CAS_change_P6 R/W 0x1 Mask Tx_CAS_change_P6 interrupt.
[20] Tx_CAS_change_P5 R/W 0x1 Mask Tx_CAS_change_P5 interrupt.
[19] Tx_CAS_change_P4 R/W 0x1 Mask Tx_CAS_change_P4 interrupt.
[18] Tx_CAS_change_P3 R/W 0x1 Mask Tx_CAS_change_P3 interrupt.
[17] Tx_CAS_change_P2 R/W 0x1 Mask Tx_CAS_change_P2 interrupt.
[16] Tx_CAS_change_P1 R/W 0x1 Mask Tx_CAS_change_P1 interrupt.
[15] JBC_underrun_P8 R/W 0x1 Mask JBC_underrun_P8 interrupt.
[14] JBC_underrun_P7 R/W 0x1 Mask JBC_underrun_P7 interrupt.
[13] JBC_underrun_P6 R/W 0x1 Mask JBC_underrun_P6 interrupt.
[12] JBC_underrun_P5 R/W 0x1 Mask JBC_underrun_P5 interrupt.
[11] JBC_underrun_P4 R/W 0x1 Mask JBC_underrun_P4 interrupt.
[10] JBC_underrun_P3 R/W 0x1 Mask JBC_underrun_P3 interrupt.
[9] JBC_underrun_P2 R/W 0x1 Mask JBC_underrun_P2 interrupt.
[8] JBC_underrun_P1 R/W 0x1 Mask JBC_underrun_P1 interrupt.
[7] Rx_CAS_change_P8 R/W 0x1 Mask Rx_CAS_change_P8 interrupt.
[6] Rx_CAS_change_P7 R/W 0x1 Mask Rx_CAS_change_P7 interrupt.
[5] Rx_CAS_change_P6 R/W 0x1 Mask Rx_CAS_change_P6 interrupt.
[4] Rx_CAS_change_P5 R/W 0x1 Mask Rx_CAS_change_P5 interrupt.
[3] Rx_CAS_change_P4 R/W 0x1 Mask Rx_CAS_change_P4 interrupt.
[2] Rx_CAS_change_P3 R/W 0x1 Mask Rx_CAS_change_P3 interrupt.
[1] Rx_CAS_change_P2 R/W 0x1 Mask Rx_CAS_change_P2 interrupt.
[0] Rx_CAS_change_P1 R/W 0x1 Mask Rx_CAS_change_P1 interrupt.
Rx_CAS_change 0x40+(port-1)*4
Bits Data Element Name R/W
Reset
Value
Description
[31:0] Rx_CAS_change R/W 0x0000
0000
Bit 31 represents timeslot 31 and bit 0 represents timeslot
0 for the port. When a bit is set it indicates a change in
received CAS (from the Ethernet port) in the
corresponding timeslot. The current CAS bits can be read
from the appropriate Rx_Line_CAS reg
ister (section
11.4.10). Se
e section.10.6.5.2
JBC_underrun 0x80+(port-1)*4
Bits Data Element Name R/W
Reset
Value
Description
[31:0] JBC_underrun R/W 0x0000
0000
Bit 31 represents timeslot 31 and bit 0 represents timeslot
0 for the port. When a bit is set it indicates a jitter buffer
underrun for the corresponding timeslot.
JBC_underrun_mask 0x84+(port-1)*8
Bits Data Element Name R/W
Reset
Value
Description
[31:0] JBC_underrun_mask R/W 0xFFFF
FFFF
Each bit masks an interrupt caused by the corresponding
bit in the
3JBC_underrun register.