Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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11.4.13 Receive SW CAS
The base address for the TDMoP Rx software CAS register space is 0x58,000. These registers specify the CAS
signaling bits the TDMoP block transmits on the TDMn_TSIG signals during unassigned timeslots and during
timeslots where CAS is not assigned. See section 10.6.5.2 for more details.
In the regi
ster descriptions in this section, the index port indicates port number: 1-8 for DS34T108, 1-4 for
DS34T104, 1-2 for DS34T102, 1 only for DS34T101. The index ts indicates timeslot number: 0 to 31.
Table 11-14. Receive SW CAS Registers
Addr
Offset
Register Name Description Page
Port 1
0x000 Rx_SW_CAS_TS0 Rx software conditioning for timeslot 0 for Port 1 206
0x000+ts*4 Rx_SW_CAS_TS[ts] Rx software conditioning for timeslot ts for Port 1 206
0x07C Rx_SW_CAS_TS31 Rx software conditioning for timeslot 31 for Port 1 206
Port 2
0x080 Rx_SW_CAS_TS0 Rx software conditioning for timeslot 0 for Port 2 206
0x080+ts*4 Rx_SW_CAS_TS[ts] Rx software conditioning for timeslot ts for Port 2 206
0x0FC Rx_SW_CAS_TS31 Rx software conditioning for timeslot 31 for Port 2 206
Port 3
0x100 Rx_SW_CAS_TS0 Rx software conditioning for timeslot 0 for Port 3 206
0x100+ts*4 Rx_SW_CAS_TS[ts] Rx software conditioning for timeslot ts for Port 3 206
0x17C Rx_SW_CAS_TS31 Rx software conditioning for timeslot 31 for Port 3 206
Port 4
0x180 Rx_SW_CAS_TS0 Rx software conditioning for timeslot 0 for Port 4 206
0x180+ts*4 Rx_SW_CAS_TS[ts] Rx software conditioning for timeslot ts for Port 4 206
0x1FC Rx_SW_CAS_TS31 Rx software conditioning for timeslot 31 for Port 4 206
Port 5
0x200 Rx_SW_CAS_TS0 Rx software conditioning for timeslot 0 for Port 5 206
0x200+ts*4 Rx_SW_CAS_TS[ts] Rx software conditioning for timeslot ts for Port 5 206
0x27C Rx_SW_CAS_TS31 Rx software conditioning for timeslot 31 for Port 5 206
Port 6
0x280 Rx_SW_CAS_TS0 Rx software conditioning for timeslot 0 for Port 6 206
0x280+ts*4 Rx_SW_CAS_TS[ts] Rx software conditioning for timeslot ts for Port 6 206
0x2FC Rx_SW_CAS_TS31 Rx software conditioning for timeslot 31 for Port 6 206
Port 7
0x300 Rx_SW_CAS_TS0 Rx software conditioning for timeslot 0 for Port 7 206
0x300+ts*4 Rx_SW_CAS_TS[ts] Rx software conditioning for timeslot ts for Port 7 206
0x37C Rx_SW_CAS_TS31 Rx software conditioning for timeslot 31 for Port 7 206
Port 8
0x380 Rx_SW_CAS_TS0 Rx software conditioning for timeslot 0 for Port 8 206
0x380+ts*4 Rx_SW_CAS_TS[ts] Rx software conditioning for timeslot ts for Port 8 206
0x3FC Rx_SW_CAS_TS31 Rx software conditioning for timeslot 31 for Port 8 206
Rx_SW_CAS 0x000+(port-1)*0x80+ts*4
Bits Data Element Name R/W
Reset
Value
Description
[31:4] Reserved - 0x0 Must be set to zero
[3:0] Rx_CAS R/W None CAS signaling (ABCD) transmitted towards TDMn_TSIG
when Rx_CAS_src=1 in Bundle Configuration Tables.
Must be differe
nt from 0000.