Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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11.4.8 Jitter Buffer Control
The base address for the TDMoP jitter buffer control is 0x30,000.
In the register descriptions in this section, the index port indicates port number: 1-8 for DS34T108, 1-4 for
DS34T104, 1-2 for DS34T102, 1 only for DS34T101. The index ts indicates timeslot number: 0 to 31. The index n
indicates the bundle number: 0 to 63. See section 10.6.10 for more information.
Table 11
-8. Jitter Buffer Status Table
Addr
Offset
Register Name Description Page
0x000 Status_and_level[1, 0] Jitter buffer port 1 timeslot 0 status and fill level 197
0x004 Min_and_max_level[1, 0] Jitter buffer port 1 timeslot 0 min / max levels 198
(port-1)*0x100+ts*8 Status_and_level[port, ts] Jitter buffer status and fill level 197
(port-1)*0x100+ts*8+4 Min_and_max_level[port, ts] Jitter buffer min / max levels 198
0x7F8 Status_and_level[8, 31] Jitter buffer port 8 timeslot 31 status and fill level 197
0x7FC Min_and_max_level[8, 31] Jitter buffer port 8 timeslot 31 min / max levels 198
Note 1: In high speed mode, Hs_status_and_level and Hs_min_and_max_level reside in Status_and_level0 and
Min_and_max_level0 registers, respectively.
Note 2: The CPU should never try to read Min_and_max_level from an HDLC bundle. When the CPU performs an access to
these registers, it causes some bits to be changed – bits that are used for other purposes in HDLC bundles and thus
may cause severe problems.
Table 11-9. Bundle Timeslot Table
Addr
Offset
Register Name Description Page
0xF00 Bundle_ts0 Assigned timeslots in bundle 0 197
0xF00+n*4 Bundle_ts[n] Assigned timeslots in bundle n 197
0xFFC Bundle_ts63 Assigned timeslots in bundle 63 197
11.4.8.1 Status_and_level Registers
The status_and_level registers have different fields depending on the bundle type: 3HDLC, 3Structured
AAL1/CESoPSN,
3Unstructured AAL1/SAToP or High Speed AAL1/SAToP. The subsections below describe the
status_and_level register fields for each type. In the register descriptions in this section, the index port indicates
port number: 1-8 for DS34T108, 1-4 for DS34T104, 1-2 for DS34T102, 1 only for DS34T101. The index ts indicates
timeslot number: 0 to 31.
11.4.8.1.1 HDLC
Status_and_level (port-1)*0x100+ts*8
Bits Data Element Name R/W
Reset
Value
Description
[31:2] Reserved RO 0x0 Always zero
[1:0] Status RO None The status of the bundle’s jitter buffer:
00 = jitter buffer is empty
01 = jitter buffer is OK
10 = jitter buffer is full
11 = Reserved