Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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CPU_to_TDM_q_thresh 0x5C (0x5E)
Bits Data Element Name R/W
Reset
Value
Description
an interrupt is generated. Range: 0 to 32.
11.4.6.7 Tx Return Queue
Tx_return_q_read 0x60 (0x62)
Bits Data Element Name R/W
Reset
Value
Description
[31:13] Reserved - 0x0 Must be set to zero
[12:0] Buffer ID RO None Reading from this address extracts the first buffer ID from
the CPU Tx return queue (bits [12:0]). The buffer ID
serves as the 13 MSbs of the buffer address in the
SDRAM (i.e. corresponds to H_AD[2
3:11] out of 24
SDRAM address bits).
Tx_return _q _level 0x64 (0x62)
Bits Data Element Name R/W
Reset
Value
Description
[31:6] Reserved - 0x0 Must be set to zero
[5:0] Level RO 0x0 Number of buffers currently stored in the queue. Range: 0
to 32.
Tx_return_q_thresh 0x68 (0x6A)
Bits Data Element Name R/W
Reset
Value
Description
[31:6] Reserved - 0x0 Must be set to zero
[5:0] Threshold RO 0x0
If the number of buffers in the queue is  this threshold,
an interrupt is generated. Range: 0 to 32.
11.4.6.8 Rx Return Queue
Rx_return_q_read 0x6C (0x6E)
Bits Data Element Name R/W
Reset
Value
Description
[31:13] Reserved - 0x0 Must be set to zero
[12:0] Buffer ID RO None Reading from this address extracts the first buffer ID from
the CPU Rx return queue (bits [12:0]). The buffer ID
serves as the 13 MSbs of the buffer address in the
SDRAM (i.e. corresponds to H_AD[2
3:11] out of 24
SDRAM address bits).