Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
193 of 366
CPU_to_ETH_q_level 0x1C (0x1E)
Bits Data Element Name R/W
Reset
Value
Description
[31:6] Reserved - 0x0 Must be set to zero
[5:0] Level RO 0x0 Number of buffers currently stored in the queue. Range: 0
to 32.
CPU_to_ETH_q_thresh 0x20 (0x22)
Bits Data Element Name R/W
Reset
Value
Description
[31:6] Reserved - 0x0 Must be set to zero
[5:0] Threshold RO 0x0
If the number of buffers in the queue is  this threshold,
an interrupt is generated. Range: 0 to 32.
11.4.6.4 ETH-to-CPU Pool
ETH_to_CPU_pool_insert 0x24 (0x26)
Bits Data Element Name R/W
Reset
Value
Description
[31:13] Reserved - 0x0 Must be set to zero
[12:0] Buffer ID WO None Writing to this address causes a single 13-bit buffer ID to
be inserted to the ETH-to-CPU pool. Only bits [12:0] are
written. The buffer ID serves as the 13 MSbs of the buffer
address in the SDRAM (i.e. corresponds to H_AD[2
3:11]
out of the 24 SDRAM address bits).
ETH_to_CPU_pool_level 0x28 (0x2A)
Bits Data Element Name R/W
Reset
Value
Description
[31:8] Reserved - 0x0 Must be set to zero
[7:0] Level RO 0x0 Number of buffers currently stored in the pool. These are
the buffers that are still available to the Rx arbiter. Range:
0 to 128.
ETH_to_CPU_pool_thresh 0x2C (0x2E)
Bits Data Element Name R/W
Reset
Value
Description
[31:8] Reserved - 0x0 Must be set to zero
[7:0] Threshold RO 0x0
If the number of buffers in the pool is  this threshold, an
interrupt is generated and only OAM packets are inserted
in the ETH-to-CPU queue (non-OAM packets are
discarded). Range: 0 to 128.