Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
192 of 366
TDM_to_CPU_pool_level 0x04 (0x06)
Bits Data Element Name R/W
Reset
Value
Description
[31:8] Reserved - 0x0 Must be set to zero
[7:0] Level RO 0x0 Number of buffers currently stored in the pool. These are
the buffers that are still available to the Tx payload type
machines. Range: 0 to 128.
TDM_to_CPU_pool_thresh 0x08 (0x0A)
Bits Data Element Name R/W
Reset
Value
Description
[31:8] Reserved - 0x0 Must be set to zero
[7:0] Threshold RO 0x0
If the number of buffers in the pool is  this threshold, an
interrupt is generated. Range: 0 to 128.
11.4.6.2 TDM-to-CPU Queue
TDM_to_CPU_q_read 0x0C (0x0E)
Bits Data Element Name R/W
Reset
Value
Description
[31:13] Reserved - 0x0 Must be set to zero
[12:0] Buffer ID RO None Reading from this address extracts the first buffer ID from
the TDM-to-CPU queue (bits [12:0]). The buffer ID serves
as the 13 MSbs of the buffer address in the SDRAM (i.e.
corresponds to H_AD[23:1
1] out of 24 SDRAM address
bits).
TDM_to_CPU_q_level 0x10 (0x12)
Bits Data Element Name R/W
Reset
Value
Description
[31:8] Reserved - 0x0 Must be set to zero
[7:0] Level RO 0x0 Number of buffers currently stored in the queue. These
are the buffers still waiting to be handled by the CPU.
Range: 0 to 128.
TDM_to_CPU_q_thresh 0x14 (0x16)
Bits Data Element Name R/W
Reset
Value
Description
[31:8] Reserved - 0x0 Must be set to zero
[7:0] Threshold RO 0x0
If the number of buffers in the queue is  this threshold,
an interrupt is generated. Range: 0-128
11.4.6.3 CPU-to-ETH Queue
CPU_to_ETH_q_insert 0x18 (0x1A)
Bits Data Element Name R/W
Reset
Value
Description
[31:13] Reserved - 0x0 Must be set to zero
[12:0] Buffer ID WO None Writing to this address causes a single 13-bit buffer ID to
be inserted to the CPU-to-ETH queue. Only bits [12:0] are
written. The buffer ID serves as the 13 MSbs of the buffer
address in the SDRAM (i.e. corresponds to H_AD[2
3:11]
out of the 24 SDRAM address bits).