Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
191 of 366
11.4.6 CPU Queues
The pools and queue referred to in this section are shown in the block diagram in Figure 10-49. Whenever a queue
or pool level exceeds the associated threshold register, a latched status bit is set in the CPU_Queues_change
regi
ster which generates an interrupt unless masked by the associated mask bit in the CPU_Queues_mask
regi
ster.
In this section the address offsets in parentheses apply when the CPU data bus is 16 bits wide (pin
DAT_32_16_N=0). The base address for the TDMoP CPU queues is 0x20,000.
Table 11-7. CPU Queues
Addr
Offset
Register Name Description Page
0x00 (0x02) 3TDM_to_CPU_pool_insert Write to insert a buffer ID into the TDM-to-CPU Pool 191
0x04 (0x06) 3TDM_to_CPU_pool_level Number of buffers stored in the TDM-to-CPU Pool 192
0x08 (0x0A) TDM_to_CPU_pool_thresh TDM-to-CPU Pool interrupt threshold 3192
0x0C (0x0E) 3TDM_to_CPU_q_read Read to get a buffer ID from the TDM-to-CPU Queue 192
0x10 (0x12) 3TDM_to_CPU_q_level Number of buffers in the TDM-to-CPU Queue 192
0x14 (0x16) 3TDM_to_CPU_q_thresh TDM-to-CPU Queue interrupt threshold 192
0x18 (0x1A) 3CPU_to_ETH_q_insert Write to insert a buffer ID into the CPU-to-ETH Queue 192
0x1C (0x1E) 3CPU_to_ETH_q_level Number of buffers in the CPU-to-ETH Queue 193
0x20 (0x22) 3CPU_to_ETH_q_thresh CPU-to-ETH Queue interrupt threshold 193
0x24 (0x26) 3ETH_to_CPU_pool_insert Write to insert a buffer ID into the ETH-to-CPU Pool 193
0x28 (0x2A) 3ETH_to_CPU_pool_level Number of buffers stored in the ETH-to-CPU Pool 193
0x2C (0x2E) 3ETH_to_CPU_pool_thresh ETH-to-CPU Queue interrupt threshold. 193
0x30 (0x32) 3ETH_to_CPU_q_read Read to get a buffer ID from the ETH-to-CPU Queue 194
0x34 (0x36) 3ETH_to_CPU_q_level Number of buffers in the ETH-to-CPU Queue. 194
0x38 (0x3A) 3ETH_to_CPU_q_thresh ETH-to-CPU Queue interrupt threshold 194
0x54 (0x56)
Error! Reference source
not f
ound.
Write to insert a buffer ID into the CPU-to-TDM Queue
Error!
Bookmark
not defined.
0x58 (0x5A)
Error! Reference source
not f
ound.
Number of buffers stored in the CPU-to-TDM Queue
Error!
Bookmark
not defined.
0x5C (0x5E) 3CPU_to_TDM_q_thresh CPU-to-TDM Queue interrupt threshold 194
0x60 (0x62) 3Tx_return_q_read Read to get a buffer ID from the CPU-Tx-return Queue 195
0x64 (0x66) 3Tx_return _q _level Number of buffers stored in the CPU-Tx-return Queue 195
0x68 (0x6A) 3Tx_return_q_thresh CPU-Tx-return Queue interrupt threshold 195
0x6C (0x6E) 3Rx_return_q_read Read to get a buffer ID from the CPU-Rx-return Queue 195
0x70 (0x72) 3Rx_return_q_level Number of buffers stored in the CPU-Rx-return Queue 196
0x74 (0x76) 3Rx_return_q_thresh CPU-Rx-return Queue interrupt threshold 196
11.4.6.1 TDM-to-CPU Pool
TDM_to_CPU_pool_insert 0x00 (0x02)
Bits Data Element Name R/W
Reset
Value
Description
[31:13] Reserved - 0x0 Must be set to zero
[12:0] Buffer ID WO None Writing to this address causes a single 13-bit buffer ID to
be inserted to the TDM-to-CPU pool. Only bits [12:0] are
written. The buffer ID serves as the 13 MSbs of the buffer
address in the SDRAM (i.e. corresponds to H_AD[2
3:11]
out of the 24 SDRAM address bits).