Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Figure 6-2. TDM Cross-Connection Block Diagram
TDMoPacket
TX Interface
Framer TX
Interface
TDMn_TCLK
MODE
TDMn_TCLK pin
1
0
ref_clk[n]
TDM1_TX (Data)
TDM8_TX (Data)
FRMRn[2:0]
1
0
TSERn pin
MODE
Framer n TSER (Data)
TDMn_TX_SYNC
MODE
TDMn_TX_SYNC pin
1
0
tsync_ref[n]
1
0
Framer n TCLK
TCLKFn pin
FRMRn[2:0]
ref_clk[1]
ref_clk[8]
TDM1_TSIG_CTS
TDMn_TX_MF
MODE
1
0
TDMn_TX_MF_CD pin
FRMRn[2:0]
TDM8_TSIG_CTS
1
0
MODE
Framer n TSIG
1
0
Framer n TSYSCLK
MODE
MODE
TSYSCLKn/ECLKn pin
1
0
Framer n T(S)SYNC in
TSYNCn/TSSYNCn pin
FRMRn[2:0]
tsync_ref[1]
tsync_ref[8]
MODE
tsync_ref[n]
TDMn_RX (Data)
1
0
TDMn_RX pin
MODE
Framer 1 RSER (Data)
Framer 8 RSER (Data)
TDMn_RCLK
MODE
TDMn_RCLK pin
1
0
0
1
CLKMODE
0
1
TDMRCLKSn
TCLKOn pin
TDMIn[2:0]
Framer 1 RCLK
Framer 8 RCLK
TDMIn[2:0]
TDMIn[2:0]
ref_clk[1]
ref_clk[8]
TDMn_RX_SYNC
1
0
TDMn_RX_SYNC pin
MODE
UNFRMMODE
0
1
CLKMODE
Framer 1 RF/MSYNCn
TDMIn[2:0]
Framer 8 RF/MSYNCn
TDMIn[2:0]
tsync_ref[1]
tsync_ref[8]
TDMn_RSIG_RTS
1
0
TDMn_RSIG_RTS pin
MODE
UNFRMMODE
Framer 1 RSIG
TDMIn[2:0]
Framer 8 RSIG
1
0
MODE
Framer n RSYNC in
RSYNCn pin
CLKMODE
tsync_ref[n]
Framer RX
Interface
TDMoPacket
RX Interface
Clock
Data
F/MSYNC
Signaling
Clock
Data
F/MSYNC
Signaling
Clock
Data
F/MSYNC
Signaling
Clock
Data
F/MSYNC
Signaling
TSYSCLKn/ECLKn pins
8
RCLKn
8
TDMn_ACLK pins
8
E1CLK
T1CLK
ref_clk[n]
CLKCNTLn[4:0]
1 per Port
Port n shown
TDMn_CD
Framer n TSYNC out
Framer n RSYNC out
1
0
MODE
Framer n RSYSCLK
RSYSCLKn pin
ref_clk[n]
Note: All named control signals in this
diagram come from global registers
GCR1, GCR2, and FMRTOPISM1-4.
MODE=GCR1.MODE & !GCR1.INTMODEn.
MODE=0: Internal Mode
MODE=1: External Mode
CLOCKMODE=0: 1 Clock Mode
CLOCKMODE=1: 2 Clock Mode
SYNCNTLn[2:0]
Framer 1 TSYNC out
Framer 8 TSYNC out
tsync_ref[n]