Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
165 of 366
Port[n]_cfg_reg 0x08+n*4
Bits Data Element Name R/W
Reset
Value
Description
In two-clock mode (Two-clocks=1) this field specifies the
TDMn_TCLK edge o
n which TDMn_TX_SYNC,
TDMn_TX_MF_CD are sampled and the edge on which
TDMn_TX and
TDMn_TSIG_CTS are updated. The
Rx_sample field (above) specifies the TDMn_RCLK edge
for the Rx-side signals.
0 = Inputs sampled on the falling edge, outputs updated
on the rising edge
1 = Inputs sampled on the rising edge, outputs updated
on the falling edge
See the timing diagrams in Figure 14-15 throug
h
Figure 14-20.
[4] Two_clocks R/W 0x1
One-clock or two-clock mode.
0 = one-clock mode: TDMn_TCLK is used for both R
x and
transmit interfaces
1 = two-clock mode: TDMn_RCLK is used for the Rx
interface and TDMn_TCLK is used for the tra
nsmit
interface.
Note: (Port 1 only) This bit must be set in high-speed
mode (i.e. when 3General_cfg_reg0.High_speed=1).
[3:2] Int_framed_type R/W 0x0
Interface Framing Type
00 = Unframed (no frame sync, no multiframe sync)
01 = Framed (frame sync only, no multiframe sync)
10 = Multiframe (E1), SF (T1) (sync and mf sync)
11 = ESF(T1) (frame sync and multiframe sync)
Changing value from 10 or 11 to 00 or 01 must be
performed only after asserting the RST_SYS_N pi
n.
[1:0] Int_type R/W 0x1
Interface Type
00 = Serial
01= E1
10 = T1
11 = Reserved