Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
164 of 366
Port[n]_cfg_reg 0x08+n*4
Bits Data Element Name R/W
Reset
Value
Description
[22:21] Tx_defect_modifier R/W 0x0
Used in the control word M field for packets in all bundles
associated with TDMoP port n.
[20]
Port_Rx_enable
(Rx means from Ethernet MII)
R/W 0x0
0 = Outgoing TDM traffic from Port n of the TDMoP block
is discarded (TDMn_TX and TDMn_TSIG are held high)
1 = Outgoing TDM traffic from Port n of the TDMoP block
is enabled.
Note: (Port 1 only) This bit also applies in high-speed
mode, i.e. when
3General_cfg_reg0.High_speed=1.
[19] CTS R/W 0x1
When the Int_type field (below) specifies a serial
interface, the value of the TDMn_TSIG_CTS pin--which
behaves as CTS (Clear To Send)—comes from this field.
[18] CD_en R/W 0x0
When the Int_type field (below) specifies a serial
interface, this field is the output enable control for the CD
(Carrier Detect) function of the TDMn_TX_MF_CD pin.
When this pin is active, the output state of the
TDMn_TX_MF_CD pin comes from the CD field (below).
[17] CD R/W 0x1
When the Int_type field (below) specifies a serial
interface, the value of the TDMn_TX_MF_CD pin—
which
behaves as CD (Carrier Detect)—comes from this field
when the CD_en bit (above) is high.
[16] Loss R/W 0x0
Loss of sync on TDM port n. Causes the L bit in the
control word to be set for packets in all bundles
associated with TDMoP port n.
[15:11] Adapt_JBC_indx R/W 0x00
Index of the jitter buffer used by the clock recovery block
to generate the clock for TDMoP port n.
[10:9] SF_to_ESF_low_CAS_bits R/W 0x0
In the case where a SF (superframe) formatted T1 is
connected by a structured-with-CAS bundle to an ESF
interface, this field is the source of the C and D CAS bits
for the ESF interface (in the Ethernet-to-TDM direction).
See section 10.6.5.
[8] TSA_act_blk R/W 0x0
0 = TSA bank1 is the active bank for Port n.
1 = TSA bank2 is the active bank for Port n.
Swapping banks takes effect at the next sync input
assertion
[7]
Port_Tx_enable
(Tx mean toward Ethernet MII)
R/W 0x0
0 = Incoming TDM traffic to Port n of the TDMoP block is
discarded
1 = Incoming TDM traffic to Port n of the TDMoP block is
enabled
Note: (Port 1 only) This bit also applies in high-speed
mode, i.e. when
3General_cfg_reg0.High_speed=1.
[6] Rx_sample R/W 0x1
In one-clock mode (Two_clocks field below is 0) this field
is ignored. In two-clock mode (Two_clocks=1) this field
specifies the TDMn_RCLK e
dge on which TDMn_RX,
TDMn_RX_SYNC an
d TDMn_RSIG_RTS are sampled.
0 = falling edge
1 = rising edge
See the timing diagrams in Figure 14-17 throug
h
Figure 14-20.
[5] Tx_sample R/W 0x0
In one-clock mode
(Two-clocks field below is 0) this field
specifies the TDMn_TCLK ed
ge on which
TDMn_TX_SYNC,
TDMn_TX_MF_CD, TDMn_RX,
TDMn_RX_SYNC and TDMn_RSIG_RTS are
sampled and the edge on which TDMn_TX a
nd
TDMn_TSIG_CTS are updated.
0 = Inputs sampled on the falling edge, outputs updated
on the rising edge
1 = Inputs sampled on the rising edge, outputs updated
on the falling edge