Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Addr
Offset
Register Name Description Page
110 Port2_status_reg1 Port 2 status bit register 1 174
114 Port2_status_reg2 Port 2 status bit register 2 174
118 Port3_status_reg1 Port 3 status bit register 1 174
11C Port3_status_reg2 Port 3 status bit register 2 174
120 Port4_status_reg1 Port 4 status bit register 1 174
124 Port4_status_reg2 Port 4 status bit register 2 174
128 Port5_status_reg1 Port 5 status bit register 1 174
12C Port6_status_reg2 Port 5 status bit register 2 174
130 Port6_status_reg1 Port 6 status bit register 1 174
134 Port6_status_reg2 Port 7 status bit register 2 174
138 Port7_status_reg1 Port 7 status bit register 1 174
13C Port7_status_reg2 Port 7 status bit register 2 174
140 Port8_status_reg1 Port 8 status bit register 1 174
144 Port8_status_reg2 Port 8 status bit register 2 174
11.4.1.1
TDMoP Configuration Registers
General_cfg_reg0 0x00
Bits Data Element Name R/W
Reset
Value
Description
[31] Discard_ip_checksum_err R/W 0x0
Indicates to discard packets received with a wrong IP
checksum. See section 10.6.13.
[30:27] Packet_trailer_length R/W 0x0
The length of the trailer attached to all received and
transmitted packets. Allowed values: 0–12 (decimal).
When set to zero no trailer is attached. See section
10.6.14.
[26] Clock_recovery_en R/W 0x0
0 = Clock recovery block is disabled (power saving mode)
1 = Normal operation
Should be cleared to reduce the chip power consumption
when adaptive clock recovery is not used. When cleared,
the clock recovery registers (offset 0x48,000) must not be
accesse
d by the CPU because the clock recovery block
does not assert H_READY_N. See section 10.4.
[25:16] Rx_fifo_priority_lvl R/W 0x100
Rx FIFO threshold level in dwords. If the Rx FIFO level is
higher than this threshold, then the Rx_fifo receives the
higher priority instead of the cross-connect queue.
This parameter is relevant only when there are bundles
configured as cross-connect. The recommended value is
0x3FF (maximal value). See section 10.6.11.5.
[15:14] MII_mode_select R/W 0x0
00 = MII
01 = RMII
10 = Reserved
11 = Source sync SMII (SSMII)
[13:12] Reserved R/W 0x0 Must be set to zero
[11] High_speed R/W 0x0
0 = All ports active in E1/T1/J1 mode
1 = Port1 enabled in high-speed E3/T3/STS-1 mode, all
other ports disabled
[10] OAM_timestamp_resolution R/W 0x1
0 = OAM timestamp is incremented every 1s
1 = OAM timestamp is incremented every 100s
See section 10.6.13.6.
[9:8] Reserved R/W 0x0 Must be set to zero
[7] Mem_size R/W 0x0
SDRAM size:
0 = 64 Mb
1 = 128 Mb