Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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11.4.1 Configuration and Status Registers
The base address for the TDMoP configuration and status registers is 0x0,000.
Table 11-4. TDMoP Configuration Registers
Addr
Offset
Register Name Description Page
0x00 3General_cfg_reg0 General configuration register0 161
04 3General_cfg_reg1 General configuration register1 162
08 General_cfg_reg2 General configuration register2 3163
0C Port1_cfg_reg Port 1 configuration register 163
10 Port2_cfg_reg Port 2 configuration register 163
14 Port3_cfg_reg Port 3 configuration register 163
18 Port4_cfg_reg Port 4 configuration register 163
1C Port5_cfg_reg Port 5 configuration register 163
20 Port6_cfg_reg Port 6 configuration register 163
24 Port7_cfg_reg Port 7 configuration register 163
28 Port8_cfg_reg Port 8 configuration register 163
2C 3Rst_reg Reset register 166
30 TDM_cond_data_reg TDM AAL1/SAToP conditioning data register 167
34 ETH_cond_data_reg Ethernet AAL1/SAToP conditioning data register 167
38 3Packet_classifier_cfg_reg0 Packet classifier configuration register0 3167
3C 3Packet_classifier_cfg_reg1 Packet classifier configuration register1 167
40 3Packet_classifier_cfg_reg2 Packet classifier configuration register2 167
44 3Packet_classifier_cfg_reg3 Packet classifier configuration register3 168
48 3Packet_classifier_cfg_reg4 Packet classifier configuration register4 169
4C 3Packet_classifier_cfg_reg5 Packet classifier configuration register5 169
50 Packet_classifier_cfg_reg6 Packet classifier configuration register6 169
54 3Packet_classifier_cfg_reg7 Packet classifier configuration register7 169
58 3Packet_classifier_cfg_reg8 Packet classifier configuration register8 170
5C 3Packet_classifier_cfg_reg9 Packet classifier configuration register9 170
60 3Packet_classifier_cfg_reg10 Packet classifier configuration register10 170
64 3Packet_classifier_cfg_reg11 Packet classifier configuration register11 170
68 3Packet_classifier_cfg_reg12 Packet classifier configuration register12 170
6C 3Packet_classifier_cfg_reg13 Packet classifier configuration register13 171
70 3Packet_classifier_cfg_reg14 Packet classifier configuration register14 171
74 3Packet_classifier_cfg_reg15 Packet classifier configuration register15 171
78 3Packet_classifier_cfg_reg16 Packet classifier configuration register16 171
7C 3Packet_classifier_cfg_reg17 Packet classifier configuration register17 171
80 Packet_classifier_cfg_reg18 Packet classifier configuration register18 171
D4 3CPU_rx_arb_max_fifo_level_reg Rx arbiter maximum FIFO level register 172
Table 11-5. TDMoP Status Registers
Addr
Offset
Register Name Description Page
0xE0 General_stat_reg General latched status register 173
E4 3Version_reg TDMoP version register 173
E8 Port1_sticky_reg1 Port 1 latched status register 173
EC Port1_sticky_reg2 Port 2 latched status register 173
F0 Port1_sticky_reg3 Port 3 latched status register 173
F4 Port1_sticky_reg4 Port 4 latched status register 173
F8 Port1_sticky_reg5 Port 5 latched status register 173
FC Port1_sticky_reg6 Port 6 latched status register 173
100 Port1_sticky_reg7 Port 7 latched status register 173
104 Port1_sticky_reg8 Port 8 latched status register 173
108 Port1_status_reg1 Port 1 status bit register 1 174
10C Port1_status_reg2 Port 1 status bit register 2 174