Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
156 of 366
FMRTOPISM1 (Framer and TDM-over-Packet Internal Signal Manager 1) 0x18
Bits Data Element Name R/W Default Description
[4:0] CLKCNTL1 R/W 0x0 Clock Control, Port 1
In external mode (GCR1.MODE=
1) this field is ignored.
In internal mode (MODE=0), this field specifies the port 1 clock
signal, ref_clk[1]. See the ref_clk[n] signal in Figure 6-2. See also
Figure 8-2 an
d Figure 8-3.
00000 = RCLK1 (Recovered clock from LIU receiver 1)
00001 = RCLK2
00010 = RCLK3
00011 = RCLK4
00100 = RCLK5
00101 = RCLK6
00110 = RCLK7
00111 = RCLK8
01000 = TDM1_ACLK (Adaptive mode recovered clock
01001 = TDM2_ACLK from TDMoP block port 1)
01010 = TDM3_ACLK
01011 =TDM4_ACLK
01100 = TDM5_ACLK
01101 = TDM6_ACLK
01110 = TDM7_ACLK
01111 = TDM8_ACLK
10000 ECLK1 pin
10001 ECLK2 pin
10010 ECLK3 pin
10011 ECLK4 pin
10100 ECLK5 pin
10101 ECLK6 pin
10110 ECLK7 pin
10111 ECLK8 pin
11XX0 E1CLK from CLAD1
11XX1 T1CLK from CLAD2
FMRTOPISM2 (Framer and TDM-over-Packet Internal Signal Manager 2) 0x1C
Bits Data Element Name R/W Default Description
[31:29] SYNCNTL8 R/W 0x7 Synchronization Control, Port 8
See SYNCNTL1 above.
[28:24] CLKCNTL8 R/W 0x7 Clock Control, Port 8
See CLKCNTL1 above.
[23:21] SYNCNTL7 R/W 0x6 Synchronization Control, Port 7
See SYNCNTL1 above.
[20:16] CLKCNTL7 R/W 0x6 Clock Control, Port 7
See CLKCNTL1 above.
[15:13] SYNCNTL6 R/W 0x5 Synchronization Control, Port 6
See SYNCNTL1 above.
[12:8] CLKCNTL6 R/W 0x5 Clock Control, Port 6
See CLKCNTL1 above.
[7:5] SYNCNTL5 R/W 0x4 Synchronization Control, Port 5
See SYNCNTL1 below.
[4:0] CLKCNTL5 R/W 0x4 Clock Control, Port 5
See CLKCNTL1 above.