Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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GTIMR (Global Transceiver Interrupt Mask Register) 0x14
Bits Data Element Name R/W Default Description
[31:25] Not used. - 0 Must be set to zero.
[24] TDMoPIM R/W
0
TDM-over-Packet Interrupt Mask
This bit is the interrupt mask for GTISR.
TDMoPIS.
0 = Interrupt masked.
1 = Interrupt enabled.
[23:16] LIMn R/W
0
LIU Interrupt Mask n
Bit 23 is LIM8; bit 16 is LIM1. LIMn is the interrupt mask for
GTISR.LISn.
0 = Interrupt masked.
1 = Interrupt enabled.
[15:8] BIMn R/W
0
BERT Interrupt Mask (8-1).
Bit 15 is BIM8; bit 8 is BIM1. BIMn is the interrupt mask for
GTISR.BISn.
0 = Interrupt masked.
1 = Interrupt enabled.
[7:0] FIMn R/W
0
Framer Interrupt Mask (8-1).
Bit 7 is FIM8; bit 0 is FIM1. FIMn is the interrupt mask for
GTISR.F
ISn.
0 = Interrupt masked.
1 = Interrupt enabled.
FMRTOPISM1 (Framer and TDM-over-Packet Internal Signal Manager 1) 0x18
Bits Data Element Name R/W Default Description
[31:29] SYNCNTL4 R/W 0x3 Synchronization Control, Port 4
See SYNCNTL1 below.
[28:24] CLKCNTL4 R/W 0x3 Clock Control, Port 4
See CLKCNTL1 below.
[23:21] SYNCNTL3 R/W 0x2 Synchronization Control, Port 3
See SYNCNTL1 below.
[20:16] CLKCNTL3 R/W 0x2 Clock Control, Port 3
See CLKCNTL1 below.
[15:13] SYNCNTL2 R/W 0x1 Synchronization Control, Port 2
See SYNCNTL1 below.
[12:8] CLKCNTL2 R/W 0x1 Clock Control, Port 2
See CLKCNTL1 below.
[7:5] SYNCNTL1 R/W 0x0 Synchronization Control, Port 1
In external mode (GCR1.MODE=
1) this field is ignored.
In internal mode (MODE=0), this field specifies the port 1
frame/multiframe sync signal, tsync_ref[1]. See the tsync_ref[n]
signal in Figure 6-2. See als
o Figure 8-2 and Figure 8-3.
000 = TSYNC1 (i.e. TSYNC from the port 1 formatter)
001 = TSYNC2
010 = TSYNC3
011 = TSYNC4
100 = TSYNC5
101 = TSYNC6
110 = TSYNC7
111 = TSYNC8