Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
153 of 366
GCR1 (Global Control Register) 0x00
Bits Data Element Name R/W Default Description
1 = H_INT[1] forced inactive (high)
See Figure 10-63.
[0] IPI0 R/W 0 Interrupt Pin Inhibit 0
0 = H_INT[0] normal interrupt output behavior
1 = H_INT[0] forced inactive (high)
See Figure 10-63.
GCR2 (Global Control Register 2) 0x04
Bits Data Element Name R/W Default Description
[31:24] Not Used - 0 Must be set to zero.
[23:9] Not Used - 0 Must be set to zero.
[8] BRPMU R/W 0 BERT Rx Performance Monitor Update
This bit causes the Rx BERT performance monitoring registers to
be updated for all ports where local performance monitoring
update is disabled (BCR.PMU
M =1). A 0 to 1 transition causes
the performance monitoring registers to be updated with the latest
data, and the counters reset. If BRPMU goes low before the local
BERT BSR.PMS bit goes hi
gh, an update might not be
performed. This bit has no for ports where BCR.PMUM=0. T
his is
an asynchronous signal.
[7:0] LIUDn R/W 0 Line Interface Unit Disable n
Bit 7 is LIUD8; bit 0 is LIUD1. When set, each of these bits
disables the corresponding internal LIU and enables the
corresponding RCLKFn a
nd TDATFn pins for connection to an
external LIU (or other component such as an M13 mux or
SONET/SDH mapper).
0 = Internal LIU enabled
1 = Internal LIU disabled
Note: When LIUD=1, RCR3.I
DF and TCR3.ODF must be set to 1
to configure the framer and formatter for NRZ data on RDATFn
and TDATFn. Also, unused LIUs can be powered down by setting
LMCR.T
PDE and LMCR.RPDE.
GTRR (Global Transceiver Reset Register) 0x08
Bits Data Element Name R/W Default Description
[31:19] Not Used - 0 Must be set to zero.
[18] TOPRST R/W 0 TDMoP Core Software Reset
When set, this bit resets all of the TDMoP configuration registers
to their default value.
0 = Normal operation
1 = Reset the TDMoP core
[17] BSRST R/W 0 BERT Software Reset
All BERT logic and registers are reset on a 0-to-1 transition of this
bit. The reset is released when a zero is written to this bit.
0 = Normal operation
1 = Reset all BERTs
[16] FSRST R/W 0 Framer Software Reset
All framer logic and registers are reset on a 0-to-1 transition of
this bit. The reset is released when a zero is written to this bit.
0 = Normal operation
1 = Reset all framers