Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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11.3 Global Registers
Functions contained in the global registers include device ID, CLAD configuration, TDMoP to framer connections,
block resets, and block interrupt status. The global register base address is 0x108,000.
Table 11-2. Global Registers
Addr
Offset
Register Name
R/W Description Page
0x00 GCR1 R/W Global Control Register 1 151
04 GCR2 R/W Global Control Register 2 153
08 GTRR R/W Global Transceiver Reset Register 153
0C IDR RO Identification Device Register 154
10 GTISR RO Global Transceiver Interrupt Status Register 154
14 GTIMR R/W Global Transceiver Interrupt Mask Register 155
18 FMRTOPISM1 R/W Framer and TDM-over-Packet Internal Signal Manager 1 155
1C FMRTOPISM2 R/W Framer and TDM-over-Packet Internal Signal Manager 2 156
20 FMRTOPISM3 R/W Framer and TDM-over-Packet Internal Signal Manager 3 157
24 FMRTOPISM4 R/W Framer and TDM-over-Packet Internal Signal Manager 4 158
GCR1 (Global Control Register) 0x00
Bits Data Element Name R/W Default Description
[31:24] TSSYNCPEn R/W 0 Transmit System Frame/Multiframe Sync Pin Enable
Bit 31 is TSSYNCPE8; bit 24 is TSSYNCPE1. These bits enable
the TSYNCn/TSSYNCn pin to be TSSYNCn when set. The
TSSYNCn pin should be enabled for any framer where the
transmit elastic
store is enabled.
0 = Pin is TSYNCn
1 = Pin is TSSYNCn
[23:15] INTMODEn - 0 When GCR1.MODE=0, all ports are configured for internal mode
and these bits are ignored. When GCR1.MODE=1, IN
TMODEn
configures port n as follows:
0 = External Mode
1 = Internal Mode
These bits are only available on the DS34T108. See section 8 for
details.
[14] SYSCLKS R/W 0 TDMoP System Clock Frequency Select
When a 25MHz clock is applied to the CLK_SYS pin (i.e.
when
the CLK_SYS_S pin is hi
gh), this bit configures the CLAD2 block
to provide either a 50MHz clock or a 75MHz clock to the TDMoP
block. When CLK_SYS_S=0 this bit is a don’t care. See section
10.4.
0 =
50MHz
1 = 75MHz
[13:12] FREQSEL R/W 00 Frequency Select
Specifies the frequency of the signal applied to the CLK_HIGH
pin.
00 =
38.88MHz (CLAD bypass; 38.88MHz in and out).
01 = 19.44MHz
10 = 10.000MHz
11 = 77.76MHz
[11] UNFRMMODE R/W 0 Unframed Mode
Specifies framed or unframed connection between the framers
and the TDMoP block. Affects all ports. Only valid in internal
mode (GCR1.MODE=
0). Ignored in external mode. See
section 8.1.
0 =
Framed mode
1 = Unframed mode
Note: When framing is not needed, the framer still has to be setup
to bypass the framer to work properly in Unframed mode.