Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
150 of 366
Figure 11-4. Partial Data Elements (16 to 32 bits long)
SPI interface mode (
H_CPU_SPI_N=0) always uses 32-bit addressing. See section 10.3.
11.2 Top-Level Memory Map
Table 11-1. Top-Level Memory Map
Address Range Contents Page
0 – 7F,FFF TDM-over-Packet Registers 159
80,000 – 9F,FFF Reserved ---
100,000 – 107,FFF Framer, LIU and BERT Registers 224
108,000 – 108,FFF Global Registers 151
109,000 – FFF,FFF Reserved ---
1,000,000 – 1,FFF,FFF External SDRAM ---