Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
149 of 366
11 Device Registers
11.1 Addressing
Device registers and memory can be accessed either 2 or 4 bytes at a time, as specified by configuration pin
DAT_32_16_N. In the 1
6-bit addressing mode, addresses are multiples of 2, while in 32-bit addressing, addresses
are multiples of 4.
The prefix “0x” indicates hexadecimal (base 16) numbering, as does the suffix “h” (Example: 2FFh). Addresses are
always indicated in hexadecimal format.
The byte order for both addressing modes is “big-endian” meaning the most significant byte has the lowest
address. See byte order numbers in grey in Figure 11-1 and Figure 11-2.
Figure 11-1. 16-Bit Addressing
Figure 11-2. 32-Bit Addressing
31
24 23 16
0
4
8
C
ADD
15
8 7
0
H_WR_BE3_N H_WR_BE2_N
H_WR_BE1_N
H_WR_BE0_N
Partial data elements (shorter than 16 or 32 bits) are always positioned from LSb to MSb with the rest of the bits
left unused. Thus, the bit numbers of data elements shorter than 16 bits are identical for both addressing modes
(see bits [12:0] in Figure 11-3) and the
CPU can access all bits by a single read/write.
Figure 11-3. Partial Data Elements (shorter than 16 bits)
Data elements 17 to 32 bits long need one read/write access in 32-bit addressing and two in 16-bit addressing. In
Figure 11-4, t
he 20-bit data element needs one 32-bit CPU access (bits [19:0]) and two 16-bit accesses (bits [15:0]
and then [3:0]).