Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
147 of 366
Figure 10-80. Repetitive Pattern Synchronization State Diagram
10.14.4.3 Rx Pattern Monitoring
Rx pattern monitoring monitors the incoming data stream for both an OOS condition and bit errors and counts the
incoming bits. An Out Of Synchronization (BSR.OO
S=1) condition is declared when the synchronization state
machine is not in the Sync state. An OOS condition is terminated when the synchronization state machine is in the
Sync state. A change of state of the OOS status bit sets the BSRL:OOSL
latched status bit and can cause an
interrupt if enabled by BSRIE.OOSIE.
Bit erro
rs are determined by comparing the incoming data stream bit to the Rx pattern generator output. If they do
not match, a bit error is declared (BSRL:BEL=1), an
d the bit error and bit counts are incremented. If they match,
only the bit count is incremented. The bit count and bit error count are not incremented when an OOS condition
exists. The setting of the BEL status bit can cause an interrupt if enabled by BSRIE.BEIE.
10.14.5 BERT Transmit Pattern Generation
The pattern generator generates the outgoing test pattern. The transmit pattern generator is a 32-bit shift register
that shifts data from the least significant bit (LSB, bit 1) to the most significant bit (MSB, bit 32). The input to bit 1 is
the feedback. For a PRBS pattern (generating polynomial x
n
+ x
y
+ 1), the feedback is an XOR of bit n and bit y.
For a repetitive pattern (length n), the feedback is bit n. The values for n and y are individually programmable (1 to
32, y < n) in the BPCR.PL
F and PTF fields. The output of the Rx pattern generator is the feedback. If QRSS is
enabled (BPCR:Q
RSS=1), the feedback is an XOR of bits 17 and 20, and the output is forced to one if the next 14
bits are all zeros. For PRBS and QRSS patterns, the feedback is forced to one if bits 1 through 31 are all zeros.
When a new pattern is loaded, the pattern generator is loaded with a seed/pattern value before pattern generation
starts. The seed/pattern value is programmable (0 – 2
n
- 1). in the BSPR registers. The generated pattern can be
inverted by setting BCR:T
PIC.
Sync
MatchVerify
1 bit erro
r
Pattern Matches
32 bits without errors
6 of 64 bits with errors